Phase detector

Abstract

The phase detection equipment includes phase detector, phase inverting logic circuit, delay unit, latch unit and OR-logic circu8it, it is used for detecting phase between the reference signal and feedback signal and outputting a delay control signal. The phase delector can utilize reference signal to obtain state between feedback signals so as to produce detection signal, and the phase inventing logic circuit and delay unit can be used for inverting the detection signal, slightly delaying it and feeding it into latch unit so as to produce latch signal. The detection signal and latch signal are fed into OR-logic circuit, the OR-logic circuit can feed the delay control signal into counter so as to make the delay circuit meet different time delay requirements of T / 4, T / 2 and T, etc.

Description

technical field [0001] The invention belongs to a detection device, in particular to a phase detection device of a delay-locked loop. Background technique [0002] In logic circuits, it is often necessary to delay the output of signals according to design requirements. There are many ways to design a delay circuit. Using a delay-locked loop (Delay-Lock Loop DLL), the input signal can be accurately delayed by 1 / 4 cycle, half cycle or one cycle to meet different needs in circuit design. [0003] In Figure 1, a prior art solution is disclosed which illustrates the phase relationship between the reference signal and the delayed signal. As shown in FIG. 1 , the reference signal S is in the form of a square wave. If the timing of the reference signal S is delayed by 1 / 4 cycle (ie T / 4), the delayed signal SD can be formed. Therefore, the wave form of the delayed signal SD is the same as that of the reference signal S, but the phase is different by T / 4. [0004] in the attached ...

AI Technical Summary

Problems solved by technology

In other words, since the first signal is obtained by the phase detector 220, the delay time will not change. Therefore, it is naturally impossible to make the reference signal 50 meet the design requirement of delaying by one cycle.

Therefore, in terms of such delay-locked circuits, there is a wrong phase-locked range FR, that is, as long as the feedback signal 55 falls within the wrong phase-locked range FR, the correct phase-locked procedure cannot be completed, so that the circuit cannot working normally

[0012] Obviously, the disadvantage of the traditional delay-locked loop is that if two different delays of 1 / 4 cycle and 1 cycle are desired, two sets of different delay-locked loops must be established to generate different delay times respectively. It is not possible to generate these two different delays with the same DLL

In this way, it not only takes up twice the circuit area, but also increases the production cost and circuit complexity, greatly reducing the industrial applicability

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