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Nonvolatile semiconductor memory device

A storage device, non-volatile technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, information storage, etc., can solve the problems of reducing the integration of storage units and not being able to adapt to large-capacity storage devices

Inactive Publication Date: 2005-05-25
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if this is done, the degree of integration of the memory cells will be lowered, and it cannot be adapted to the increase in capacity of nonvolatile semiconductor memory devices in recent years.

Method used

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  • Nonvolatile semiconductor memory device
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  • Nonvolatile semiconductor memory device

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0051] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0052] (memory cell structure)

[0053] figure 1 showing a cross-section of a nonvolatile semiconductor memory device, figure 2 is its equivalent circuit diagram. figure 1 Among them, one memory cell 100 has: a word gate 104 formed of a material including polysilicon through a gate oxide film on a p-type well 102 region on a silicon substrate; a nonvolatile gate 104 including a control gate 106A. memory element (MONOS memory cell) 108A; and memory element (MONOS memory cell) 108B including the control gate 106B.

[0054] The two control gates 106A and 106B are formed on two side walls of the word gate 104, and are electrically insulated from the word gate 104, respectively.

[0055] Each of the two storage elements 108A, 108B is configured between one of the two control gates 106A, 106B corresponding to M (metal) of MONOS and the p-type well 102 corresponding to S ...

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PUM

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Abstract

The non-volatile semiconductor storage device has a memory cell array area and a first and a second selection area, wherein the memory cell array area is respectively arranged in a plurality of 2 gates controlled by a word gate and a control gate in the first and second directions. A storage unit of a MONOS storage unit. The memory cell array region has: a plurality of sub-bit lines formed along the first direction with impurity layers extending to the first and second selection regions; a plurality of sub-control gate lines extending along the first direction; and For the plurality of word lines extending in the second direction, the first and second selection regions have sub-bit selection circuits for selectively connecting the plurality of sub-bit lines to main bit lines whose number is smaller than the plurality of sub-bit lines.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory device including a memory cell including two nonvolatile memory elements controlled by one word gate and two control gates. Background technique [0002] As a nonvolatile semiconductor device, there is known a MONOS in which the gate insulating layer between the channel and the gate is composed of a laminated body of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and the silicon nitride film traps charges. (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type. [0003] This MONOS type nonvolatile semiconductor memory device is disclosed in "2000 Symposium on VLSI Technology Digest of Technical Papers" (2000 Symposium on VLSI Technology Digest of Technical Papers) by Y. Hayashi et al. , discloses a dual MONOS flash memory cell with 2 non-volatile storage elements (MONOS memory cells) controlled by 1 word gate and 2 control gates. That is, 1 flash memory ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/04G11C16/06H01L21/8247H01L29/788H01L29/792H10B69/00
CPCG11C16/0441
Inventor 大轮义仁
Owner SEIKO EPSON CORP