Multiple frequency output clock pulse signal synthesizer and its synthesis method

Abstract

The multiple frequency output time pulse signal synthesizer and its synthesis method is used in converter to convert progressive scanned image data into interlaced scanned image data. The converter provides one first frequency F1 reference time pulse signal. The time pulse signal synthesizer includes phase-locked loop vibrator, frequency dividing feedback circuit, the first frquency dividing output circuit and the second frequency dividing output circuit. The time pulse signal synthesizing process includes receiving the first frequency F1 reference time pulse signal of frequency F1 to output one time pulse signal of frequency F1xN; and diving the clock pulse signal of frequency F1xN to output one first output time pulse signal of frequency F1xN / P1 and one second output time pulse signal of frequency F1xN / P2 with the P2 / P1 value being regulated based on horizontal scanning line pixel number ratio between the progressive data and the interlaced data.

Description

technical field [0001] The invention relates to a multi-frequency output clock signal synthesizer and a clock signal synthesis method, in particular to a multi-frequency output clock signal synthesizer and a clock signal synthesis method applied in a television signal encoder. Background technique [0002] With the rapid development of manufacturing technology, personal computer has become a necessary product for people's life, and it has powerful computing power, and users can use it to complete the functions of many other electronic products. Utilizing a personal computer to play laser video discs such as VCD and DVD is an example, but usually because the size of the display screen of the personal computer is too small, it is inconvenient to actually watch it. Important function of graphics cards in personal computers. [0003] FIG. 1(a) is a partial functional block diagram of a display adapter, in which a graphics processing chip 10 (graphic chip) outputs a parallel dig...

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Problems solved by technology

[0008] But because there is only a phase-locked loop clock generator 127 in the TV signal encoder 12 to generate the clock signal to provide to the picture size adjustment and anti-flicker device 123 and NTSC / PAL encoder 125 at the same time, so that Fsd=Fe, therefore When the screen size is adjusted and the progressive image data processed by the anti-flicker device 123 has more and more horizontal scanning line pixels (for example, 1024 points, 1152 points, 1365 points or even 1600 points), it will be displayed on the TV after processing. The image width on the screen will be narrower and narrower (because Fsd needs to increase with the increase of the number of horizontal scan line pixels, and Fe=Fsd, and too large Fe will cause the pixel output frequency of the horizontal scan line on the TV screen to be too high. fast, which in turn causes the image width to become narrower), which cannot make full use of the original effective width of the TV

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