Method and apparatus for adjusting the phase of input/ output circuitry

Abstract

Input / output clockphase adjustment circuitry for use with input / output circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an input / output clock coupled to be received by an input / output circuit of an integrated circuit chip for input / output data transfers in a system. The phase adjustment circuit includes a phase locked loop circuit coupled to receive the system clock through a first delay circuit. The input / output clock generated by the phase locked loop circuit is received through a second delay circuit at a feedback clock input of the phase locked loop circuit. The first and second delay circuits are used to control the phase of the input / output clock generated by the phase locked loo circuit relative to the system clock. In one embodiment, a third delay circuit is included in an input / output data path of the input / output circuit of the integrated circuit. The third delay circuit enables input and output data transmission from the integrated circuit to be clocked out of phase with the system clock.

Description

technical field [0001] The present invention relates generally to the field of integrated circuits, and more particularly, the present invention relates to input / output between integrated circuit chips. Background technique [0002] Currently, input / output (I / O) timing testing of integrated circuit chips, such as central processing units (CPUs), is performed using testers. The I / O timing of all pins can be tested using a carefully calibrated multichannel tester, where the tester and the on-chip phase-locked loop (PLL) share the same clock. The I / O timing specified by the specification is obtained by exercising different "worst case" patterns programmed during tester setup. Furthermore, the tester environment is designed to simulate the real system environment as closely as possible. [0003] Measuring I / O timing in a tester environment has several disadvantages. To get very accurate readings, all tester channels require extremely tight timing and careful calibration, addi...

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Problems solved by technology

Also, it has been observed that a significant portion of parts that fail the I / O timing test are rejected due to relatively small variances

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