Interleave address generator

A technology of address generation and address, applied in the direction of responding to error generation, using interleaving technology for error correction/detection, redundant code for error detection, etc., can solve problems such as large processing burden, processing delay, and large burden of interleaving patterns

Inactive Publication Date: 2002-08-28
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0064] Yet, in above-mentioned existing interleave address generating method, all need carry out modulo operation when seeking basic column interleave pattern {c(i)}, and when seeking the column interleave pattern of each row, so have following problem: generate interleave address The amount of calculation required is large, and the burden of generating interlaced patterns is large
For example, in the case of interleaving length K=1000, when finding the basic column interleaving pattern and the column interleaving pattern of each row, 20*52=1040 times of modular operations are required respectively, so when the interleaving length is large, the processing load is particularly Big
[0065] In addition, in the circuit for generating the above-mentioned interleaving address, modulo calculations are required when obtaining the basic column interleaving pattern {c(i)} and when obtaining the column interleaving pattern of each row, so there is the following problem: how many cycles of operation, processing delays occur

Method used

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Embodiment 1

[0146] Fig. 7 is a block diagram showing the structure of an interleaving address generation device according to Embodiment 1 of the present invention. As shown in the figure, the interleave address generation device of this embodiment has: row counter 11, memory address generation device 12, memory 13 (second storage unit), memory 14 (first storage unit), multiplier 15 (address offset shift calculation unit), an adder 16, and a size comparison unit 17. On the other hand, the memory address generation device 12 has a memory 21 (third storage means), a selector 22 , an adder 23 , a comparison and difference device 24 , a selector 25 , and a FIFO 26 .

[0147] The row counter 11 sequentially outputs the row numbers of each row from the first row to the memory 14 and the memory 12 . In this case, in the case of outputting the row number of the Mth row, j=M-1 is output. That is, first, the row numbers j=0 to j=R-1 of the first column are output, and then the row numbers j=0 to j...

Embodiment 2

[0165] In Embodiment 2, a turbo encoding apparatus having the interleaving address generating apparatus of Embodiment 1 will be described. Fig. 11 is a block diagram showing the structure of a turbo encoding device according to the second embodiment.

[0166] The turbo encoding device 40 of this embodiment includes: recursive organization convolutional encoders 41 , 43 , and an interleaver 42 .

[0167] The recursive tissue convolutional encoder 41 encodes the input information sequence with a recursive tissue convolutional code. The interleaver 42 performs the interleaving described in the first embodiment on the similarly input information sequence. The recursive convolutional encoder 43 receives the information sequence output from the interleaver 42 as input, and performs encoding of a recursive convolutional code.

[0168] Next, the operation of the turbo encoding device 40 configured as described above will be described. The information sequence input to the turbo enc...

Embodiment 3

[0173] In Embodiment 3, a turbo decoding apparatus having the interleave address generating apparatus of Embodiment 1 will be described. The turbo decoding device receives and decodes the code sequence output from the turbo coding device of the third embodiment. Fig. 12 is a block diagram showing the structure of a turbo decoding device according to the third embodiment.

[0174] The turbo decoding device 50 of this embodiment has: soft output decoders 51 , 53 , an interleaver 52 , and a deinterleaver 54 .

[0175] The soft output decoder 51 encodes the received sequence encoded by the recursive convolutional encoder 41 shown in Embodiment 2 based on prior information from the deinterleaver 54 described later, and the received sequence that is output without encoding. sequence for error correction decoding. This prior information is soft decision information of the received sequence 1 bit earlier. The interleaver 52 interleaves the output of the soft output decoder 51 using...

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Abstract

The memory address generator 12 generates a memory address, and the multiplier 15 reads out the row interleaving pattern value corresponding to the row number output from the row counter 11 from the memory 14 storing the row interleaving pattern of the matrix, and the read row interleaving pattern The value is multiplied by the column number of the above-mentioned matrix to calculate the address offset value, and the adder 16 reads out the column interleave pattern value corresponding to the memory address generated by the memory address generating device from the memory 13 storing the column interleave pattern of the above-mentioned matrix, and the The read column interleave pattern value and the above-mentioned address offset value are added to generate an interleave address.

Description

technical field [0001] The invention relates to an interleaving address generation device which can easily correct burst errors generated in communication lines through data sorting, in particular to an interleaving address generation device which can be applied to turbo code (Turbo code) error correction. Background technique [0002] World standardization of the third generation communication system is underway, and for an interleaver / deinterleaver included in a turbo encoder / decoder, Prime (prime number) interleaving is proposed and standardized. Prime interleaving is one of the non-uniform interleaving (random interleaving) required to implement a turbo encoder. In this Prime interleaving, data is written into the memory in address order, and data sorting is performed by reading out the data written in the memory in a different order from that at the time of writing. That is, in Prime interleaving, after data is written into the memory sequentia...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G11C8/00G11C29/00H03M13/27H04B14/04H04L1/00
CPCG11C8/00G11C29/70H03M13/2714H03M13/2764H03M13/2789
Inventor 池田彻哉铃木秀俊山中隆太朗栗山元
Owner PANASONIC CORP
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