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Address generating circuit

A technology of address generation and circuit, applied in the direction of electrical components, electronic switches, static memory, etc.

Inactive Publication Date: 2002-11-27
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, even if the fuse is in the cut state, there will be such a problem that an address corresponding to the non-cut state of the fuse will be generated due to erroneous data latching of the fuse cut information.

Method used

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Examples

Experimental program
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no. 1 example

[0047] FIG. 3 is a schematic diagram of an address generation circuit according to the first embodiment of the present invention.

[0048] FIG. 3(a) is a circuit diagram of an address generating circuit according to a first embodiment of the present invention. In this figure, reference numeral 11 is a PMOS transistor; reference numeral 12 is an NMOS transistor; reference numeral 13 is a fuse element; reference numeral 14 is a latch circuit; An inverter; reference numeral 16 is a second inverter forming a latch circuit; reference numeral 17 is a third inverter; and reference numeral 18 is a power-on reset circuit.

[0049] In Fig. 3(a), the PMOS transistor 11, the NMOS transistor 12 and the fuse element 13 are under power supply V DD and ground V SS sequentially connected in series. The latch circuit 14 includes a first inverter 15 and a second inverter 16, the input terminal of one inverter is connected to the output terminal of the other inverter. A connection node A of t...

no. 2 example

[0072] Figure 4 is a schematic diagram of the address generating circuit of the second embodiment of the present invention. The second embodiment of the present invention provides a circuit example of the power-on reset circuit in the first embodiment.

[0073] In this figure, elements disclosed in FIG. 3 are denoted by the same reference numerals. Further, reference numeral 19 is an inverter; reference numeral 20 is a transistor whose source and drain are connected; reference numeral 21 is a PMOS transistor; and reference numeral 32 is an inverter delay circuit.

[0074] Such as Figure 4 As shown, the power-on reset circuit 18 of the second embodiment has a structure including two PMOS transistors 21 whose sources and drains are connected to each other and are connected in parallel between the power supply VDD and the ground VSS. . A PMOS transistor with its gate connected to its drain forms a diode transistor.

[0075] Furthermore, the power-on reset circuit 18 has a ...

no. 3 example

[0089] Figure 5 is a schematic diagram of the address generating circuit of the third embodiment of the present invention. In this figure, something like figure 2 Disclosed elements are denoted by the same reference numerals. In addition, reference numeral 22 is a first power-on reset circuit; reference numeral 23 is a second power-on reset circuit; reference numeral 24 is an NMOS transistor with a low threshold; and reference numeral 25 is an NMOS transistor with a high threshold. The transistor and reference numeral 26 is a PMOS transistor.

[0090] The address generating circuit of the third embodiment of the present invention has a structure substantially similar to that of the first and second embodiments. However, the address generation circuit of the third embodiment is different in the structure of the power-on reset circuit.

[0091] Such as Figure 5 As shown, the power-on reset circuit of the third embodiment includes a first power-on reset circuit 22 for outp...

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Abstract

An address generation circuit, comprising: a first switch transistor, a second switch transistor, a fuse unit, a power-on reset circuit, and outputs a first reset signal for controlling the on / off state of the first switch transistor and a first reset signal for controlling the first switch transistor. A second reset signal for the on / off state of the two switching transistors. The address generating circuit further includes a latch circuit for latching and outputting a predetermined potential corresponding to the cut-off or non-cut state of the fuse element. The first reset signal turns on the first switch transistor in a first period immediately after the power is turned on, and keeps the first switch transistor in an off state after the first period ends. In addition, the second reset signal turns on the second switching transistor during at least a second period after the first period, and keeps the second switching transistor always in an off state after the second period ends.

Description

technical field [0001] The present invention relates to a kind of address generating circuit, especially a kind of redundant address generating circuit, is used for storing the address (hereinafter referred to as redundant address) of the damaged storage unit in a RAM (random access memory) storage unit array and in RAM A redundant address is generated when the power of the device is turned on. Background technique [0002] For example, 1(a) and 1(b) are schematic diagrams of traditional address generating circuits. [0003] FIG. 1(a) is a circuit diagram illustrating a conventional address generation circuit. In this figure, 41 is a first switching transistor including a PMOS transistor, 42 is a fuse element, 43 is a latch circuit, 44 is an inverter and 45 is a power-on reset circuit. [0004] In the conventional address generating circuit shown in FIG. 1(a), the first switching transistor 41 and the fuse element 42 are in the DD and ground V SS sequentially connected i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/22G11C17/18G11C29/00G11C29/04
CPCG11C17/18G11C29/785G11C29/00
Inventor 横関亘
Owner FUJITSU SEMICON LTD
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