Synchronization capturing appts. and synchronization capturing method
A technology of synchronous capture and counterparty, which is applied in the direction of synchronous device, synchronous device, selection device, etc., and can solve problems such as long time
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Embodiment 1
[0045] Fig. 4 is a main part block diagram showing a schematic configuration of a synchronization acquisition device according to Embodiment 1 of the present invention. In FIG. 4 , a radio receiving unit 102 performs predetermined radio processing (down-conversion, A / D conversion, etc.) on a signal received via an antenna 101 . The control unit 104 appropriately switches and inputs the received data to the first-stage processing unit 105 , the second-stage processing unit 110 , and the third-stage processing unit 115 by switching the switch 103 .
[0046] In the first-stage processing unit 105, the first search code generation unit 106 generates a first search code that is the same for all base stations. Correlation circuit 107 obtains a correlation value between the received data and the first search code. The averaging circuit 108 averages the correlation values over a plurality of time slots. The slot timing detection unit 109 detects the maximum value of the averaged c...
Embodiment 2
[0075] In the case where the frequency error of the received data is relatively large, if the cell search is performed as in Embodiment 1, then in the processing of the second stage and the third stage for many times, the timing of a plurality of time slots detected in the first stage changes from The current correct slot timing will gradually shift, and there is a possibility that the identification accuracy of the scrambling code and the detection accuracy of the timing of the scrambling code will decrease.
[0076] For example, when the frequency error is 5 ppm, an offset of about 50 nsec occurs during the elapse of 10 msec. That is, during the elapse of 10 msec, an offset of about one-fifth of a chip (chip) occurs in 1 chip (3.84 MHz).
[0077] Therefore, in the synchronization acquisition device of this embodiment, when the frequency error of the received data is relatively large, the detection of the slot timing is changed every time the processing of the second stage an...
Embodiment 3
[0090] As described in Embodiment 2, when the frequency error of the received data is relatively large, if the cell search shown in Embodiment 1 is performed, then in the processing of the second stage and the third stage multiple times, the first stage The detected multiple slot timings will gradually deviate from the current correct slot timing, and there is a possibility that the identification accuracy of the scrambling code and the detection accuracy of the scrambling code timing will decrease.
[0091] Therefore, the synchronization acquisition device of this embodiment differs from the synchronization acquisition device of Embodiment 1 in that, except for the slot timing detected in the first stage, the synchronization acquisition device of the present embodiment is delayed by a predetermined chip from the slot timing. Correlation values with the second search code are calculated at the timing at the timing and at the timing ahead of only a predetermined chip.
[0092...
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