Method and system for data and timing recovery in bi-phase coded data signal

Abstract

For data and timing recovery in a bi-phase coded data signal (data), the data signal is sampled using a sampling frequency (2.5-fbit) which is greater than the double bit frequency (fbit) of the data signal (data). The bit limits of the data signal are then determined from the sampling values thus obtained and the data bits and the corresponding bit clock pulse (clock pulse) of the data signal (data) are recovered from said limits.

Description

technical field [0001] The invention relates to a method and a device according to the preambles of the main claim. Background technique [0002] There are two types of biphase codes, so called biphase mark codes and so called biphase space codes. In biphase mark codes, logical ones are specifically encoded, while in biphase space codes, logical zeros are specifically encoded. In biphase marker codes, there is always a change of logic state between the data bits of the data signal, in the case of a logic 1 there is also a change among the data bits, and in the case of a logic 0 there is no such change. figure 2 Lines A and B illustrate this relationship. A similar idea is also applied in biphase spatial codes. [0003] In order to recover the data of such a bi-phase encoded data signal, the bit clock needs to be recovered at the receiving side. For this purpose it is known to use a phase synchronous clock generator (PLL) which is precisely locked to twice the bit frequen...

AI Technical Summary

Problems solved by technology

However, at relatively high data rates it is difficult to maintain the precise phase relationship between the required clock frequency and bi-phase data, which is necessary for reliable data decoding

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