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Detection method and apparatus for high-speed interconnected circuit

A technology for interconnecting circuits and testing data, used in electronic circuit testing, measuring devices, measuring electricity, etc., and can solve problems such as limiting testing

Inactive Publication Date: 2003-08-27
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional JTAG (ie, IEEE1149.1 standard) boundary-scan architecture limits its ability to test these higher speed digital interconnect circuits
[0004] JTAG testing of high-speed DC- and AC-coupled interconnects between integrated circuits is limited due to limitations in the testing of interconnects in the JTAG structure

Method used

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  • Detection method and apparatus for high-speed interconnected circuit
  • Detection method and apparatus for high-speed interconnected circuit
  • Detection method and apparatus for high-speed interconnected circuit

Examples

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Embodiment Construction

[0053]FIG. 1 illustrates testing the DC interconnect circuit 103 using the existing JTAG standard. The DC interconnect circuit 103 includes a terminating element (ie, pull-down resistor 106). Many other port element configurations are also possible in DC interconnect circuits. In the functional mode, the functional signal from the core circuit is output from the first IC through the JTAG boundary scan cell 101 of the first IC and through the output buffer 104 of the first IC. The functional signal is transmitted through the external DC interconnect circuit 103 and through the input buffer 105 and the JTAG boundary scan cell 102 of the second IC to the input of the functional core circuit of the second IC.

[0054] The JTAG boundary cell is transparent in functional mode, which is accomplished by loading the instruction register (IR) of the JTAG structure of the first and second IC with bypass instructions. However, when the external test (Extest) instruction is loaded into t...

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PUM

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Abstract

A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Description

[0001] Certain aspects of the present invention relate to the testing of interconnect circuits disclosed in US Patent No. 5,056,094 "Delay Fault Testing Method and Apparatus". technical field [0002] The present application generally relates to testing high speed DC and AC coupled interconnect circuits between integrated circuits by extending the instruction set and structure of the IEEE 1149.1 TAP and Boundary Scan standards (JTAG). Background technique [0003] The bandwidth of digital signal communication between integrated circuits on printed circuit boards is constantly increasing. To support this demand, new higher speed digital interconnect circuit technologies are being developed. The conventional JTAG (ie, IEEE 1149.1 standard) boundary-scan architecture limits its ability to test these higher speed digital interconnect circuits. [0004] JTAG testing of high-speed DC- and AC-coupled interconnects between integrated circuits is limited due to limitations in interc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3185G06F11/22
CPCG01R31/318552G01R31/318555G01R31/31858G01R31/28
Inventor L·D·威特赛尔
Owner TEXAS INSTR INC