Method for mfg mask ROM

Abstract

A method for processing a mask ROM provides a subslrate with a formed grating dielectric layer. A material layer is patternized after formed on the substrate covering a zone designed to form an imbedded diffusion zone then real-time vapour is used to generate a process technology or quick temper technology to turn the patternized material layer to a patternized silicon oxide layer and then form apatternized photoresist layer exposed via the silicon oxide layer to implant a doped material with the photoresist layer as the mask to form a an imbedded diffusion zone and remove the photoresist layer and form a character line on the substrate.

Description

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AI Technical Summary

Benefits of technology

The technical effect of this patented technology relates to improving the performance of Mask Read Only Memory devices while maintaining their size consistently without compromising on its reliability or functionality during fabricating processes. By forming an embedded diffused area before creation of other layers, there are no impacts from heat treatment for transistor characteristics like threshold voltage shifts caused by dopant fluctuations at high temperatures used when making these components. This results in improved stability over time with reduced variations in electrical properties such as signal delay times.

Problems solved by technology

This patented technical problem addressed in this patents relates to improving the performance of semiconductor memories such as Mask Read Only Memory (MROMs) devices while minimizing their overall dimensions. Specifically, current methods involve embedding hidden bits within certain areas of the chip's circuitry, but these techniques may lead to reduced reliability issues if there were any damage from external sources like radiation. Additionally, existing methods require multiple etch operations before depositing layers onto specific locations, increasing complexity time.

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