Method of selecting by pass of multiport register pile and equipment

Abstract

A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.

Description

technical field [0001] The present invention relates generally to processor architecture, and more particularly to selective bypassing techniques for multi-ported register files. Background technique [0002] To improve performance, current processors often use pipelining to execute instructions at very high speeds. On such processors, instruction processing is divided into a series of operations, each in its own pipeline stage. Independent operations in several instructions can be processed simultaneously by different pipeline stages, which increases the instruction throughput of the processor. A common instruction pipeline in a microprocessor consists of the following pipeline stages: Instruction Fetch (IF), Decode (Dec), Read Data (RD), Execute (EX), and Write (WR). [0003] refer to figure 1 , which illustrates the construction of a multi-operation microprocessor. As noted above, the multi-operation microprocessor includes a dual function unit (FU) architecture havin...

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It should be understood that although only a dual function unit configuration is show...

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