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Semiconductor intergrated circuit device

A technology of integrated circuits and semiconductors, applied in the manufacture of semiconductor devices, circuits, semiconductor/solid-state devices, etc., can solve problems such as insufficient realization, and achieve the effect of area reduction

Inactive Publication Date: 2004-05-26
ROHM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] However, even with such a structure, the increase in the number of terminals and the miniaturization of the semiconductor process along with the high-functioning LSI in recent years cannot fully realize the area occupied by the dummy bumps on the chip. While the load-resistant effect is required to further reduce the area

Method used

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  • Semiconductor intergrated circuit device
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  • Semiconductor intergrated circuit device

Examples

Experimental program
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Embodiment Construction

[0028] specific implementation

[0029] Below, refer to Figure 1 to Figure 6 Embodiments of the semiconductor integrated circuit device of the present invention will be described in detail.

[0030] here, image 3 , Figure 4 , Figure 5 This is an enlarged view representing four corners of a chip corner of a semiconductor integrated circuit device chip. Each figure will be described below.

[0031] image 3 It is a bump arrangement diagram showing Example 1. It is provided with a bump 3 for circuit connection connected to an internal circuit not shown, and a dummy bump 2a is provided on each side of the part closer to the corner of the chip 1 of the semiconductor integrated circuit device. , and the area of ​​the dummy bumps 2a is about twice the area of ​​the bumps 3 for circuit connection, so a total load-bearing effect equivalent to the area of ​​4 bumps 3 for circuit connection is obtained. The inner portion of the portion shown by the dotted line is an area guar...

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PUM

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Abstract

A semiconductor integrated circuit device which requires high packaging density adopts a method for forming bumps in a terminal section of a semiconductor chip and bonding the semiconductor chip directly on a substrate. In this case, in order to prevent damage to the semiconductor integrated chip, which would otherwise be caused by bonding pressure employed at the time of bonding operation, non-connected dummy bumps are provided at corner sections of the semiconductor chip. Even when the dummy bumps are provided, there arises a necessity for preventing an increase in the size of the semiconductor chips, which would otherwise arise when the dummy bumps are provided on the chip.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit device with high mounting reliability, and in particular to a face down bonding of a semiconductor integrated circuit device in which a bump having an electrical connection function is provided at a terminal portion on the surface of a semiconductor substrate. ), there is also a semiconductor integrated circuit device having a dummy bump that is not electrically connected. Background technique [0002] In recent years, with the development of high-performance electromechanical devices, semiconductor integrated circuit devices mounted on the mechanical devices are further required to have high performance and complex functions, and especially in small mechanical devices such as portable information terminals and mobile phones A method capable of high-density mounting is sought in a semiconductor integrated circuit device mounted on a computer. [0003] For this reason, the method that ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/485
CPCH01L2224/13012H01L24/81H01L2924/3511H01L2924/01002H01L2224/81801H01L2224/16H01L2924/14H01L2924/01005H01L2924/01033H01L2924/01006H01L2224/13099H01L2924/01078H01L2924/01056H01L24/10H01L24/13H01L2224/13H01L2924/00014H01L2924/00H01L2224/0401
Inventor 内贵崇
Owner ROHM CO LTD
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