Semiconductor device and mfg. method for same

Abstract

A first insulating film has a first planar surface as a lower surface. A first semiconductor chip is disposed on the first insulating film. A second insulating film is disposed on the first semiconductor chip and the first insulating film and has a second planar surface as an upper surface. A first wiring layer is disposed under the first planar surface. A second wiring layer is disposed on the second planar surface and electrically connected to the first semiconductor chip. A first conductive column penetrates the first insulating film and the second insulating film. A conductor penetrates the second insulating film.

Description

technical field [0001] The present invention relates to a semiconductor device having a high-density assembled package, and particularly relates to miniaturization and thinning of the assembled package thereof. Background technique [0002] In recent years, development of a high-density chip size package (CSF) has been intensively conducted as a semiconductor device mounting package usable in consumer equipment. Among them, the development of a stacked CSP called a system-in-package (SiP) in which a plurality of semiconductor chips are stacked in a package is also being developed. In multilayer CSP, a plurality of semiconductor chips are stacked on a substrate, and wire bonding and resin sealing are performed by wire bonding technology. Therefore, there are 2 problems. (1) It is necessary to overlap the semiconductor chips so that the pads for wire bonding of all the semiconductor chips are exposed. Therefore, due to the chip size of one semiconductor chip, there is a pro...

AI Technical Summary

Problems solved by technology

Therefore, due to the chip size of one semiconductor chip, there is a problem that other semiconductor chips are restricted by the chip size.

(2) Since the test as a CSP is performed after resin sealing without performing the test of each semiconductor chip, when the yield of each semiconductor chip is low, there is a possibility that the yield as a CSP will be significantly reduced. question

However, in these methods, there are constraints such as the need for an assembly process for each semiconductor chip, or the inability to increase the assembly density.

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