Sequencing frequency divider

Abstract

The invention provides a programmed frequency division apparatus comprising an n digit adder and an n digit type D trigger for switching an input clock into a target clock, and the input clock frequency is the m to the power of 2 times of the destination clock frequency, the adder produces a first output signal based on an adjustment parameter and a feedback signal. The type D trigger is connected with the adder to form a ring form loop for receiving a first output signal and the input clock and producing a second output signal.

Description

technical field [0001] The present invention relates to a frequency division device, in particular to a programmable frequency division device that can be controlled by computer program instructions. Background technique [0002] In a synchronous digital system, the clock signal plays a very important role. In addition to determining the performance of the system, it is also closely related to the power consumption of the circuit. In particular, modern mobile devices are all the rage. Many computer central processing units (CPUs), digital signal processors (DSPs), and microcontrollers are designed to reduce power consumption as much as possible to save power. Switches the system to a lower operating frequency when the processor is idle. [0003] For general traditional crossover devices, please refer to Figure 1A , is usually composed of an n-bit D-type flip-flop (DFlip Flop) and an incrementer (incrementer), and the different frequency signals obtained after frequency div...

AI Technical Summary

Problems solved by technology

like Figure 2B As shown, if this pulse signal is used for the clock (CLOCK), there may be a shortcoming that the duty cycle is not 50%-50%, and glitch may also occur

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