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Decapsulate method for synchronous digital series link access procedure

A link access procedure, a technology for synchronizing digital series, applied in the direction of digital transmission system, transmission system, data exchange network, etc., can solve the problems of consuming logic resources, increasing the complexity of logic programming, and reducing circuit speed.

Inactive Publication Date: 2004-08-25
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the increase in the width of the internal data bus will inevitably increase the complexity of logic programming (the complexity of logic will reduce the speed of the circuit) and consume more logic resources.
Make the running speed of the circuit difficult to reach 100M

Method used

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  • Decapsulate method for synchronous digital series link access procedure
  • Decapsulate method for synchronous digital series link access procedure
  • Decapsulate method for synchronous digital series link access procedure

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Embodiment Construction

[0023] Hereinafter, the present invention will be further described in detail through specific embodiments in conjunction with the accompanying drawings.

[0024] The decapsulation of LAPS needs to complete the following functions:

[0025] 1: X 43 +1 self-synchronizing descrambling code

[0026] 2: LAPS fixed frame

[0027] 3: Discard the rate adaptation field

[0028] 4: Discard and check the Abort field

[0029] 5: LAPS escape processing

[0030] 6: LAPS address, control, SAPI field detection

[0031] 7: CRC32 calculation

[0032] 8: Discard LAPS frame header, LAPS information payload extraction and discard frame tail

[0033] The double-byte internal data bus structure makes the processing of steps 2 to 8 more complicated. As shown in Figure 2 is a block diagram of the processing flow of the logical LAPS decapsulation method.

[0034] The function of the input interface is to receive data according to the input data valid indication signal, and the data bus width can be 16 bit...

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Abstract

This invention discloses a method for unlinking package of synchronous digital sequence link access protocol, in which, double byte or multibyte data bus and two or more serial CRC modules in same bytes with the data bus width are applied in the frame check, mid-results can be transferred between adjacent CRC modules and every one can input data and output results. Before checking, the data is processed, if they are multibyte effective data, they should be sent to two or multiple single bytes circulation redundancy check module CRC directly, if only the single one is effective, the said byte is set in one CRC, saving an 8 bit CRC module.

Description

Technical field: [0001] The invention relates to a decapsulation method for a synchronous digital series link access procedure, in particular to a synchronous digital series link access procedure framing (LAPS framing) in a decapsulation method for a synchronous digital series link access procedure ), frame check and synchronous digital series link access procedure payload extraction (LAPS payload extraction). Background technique: [0002] The present invention uses FPGA programmable logic to realize the decapsulation of the LAPS protocol, including X 43 +1 self-synchronization descrambling code, discarding rate adaptation bytes, detecting and reporting the Abort field (abort) (0x7d7e), LAPS escape processing, CRC32 check (cyclic redundancy check), and LAPS payload Extraction and generation of related alarms. The LAPS decapsulation realized by this method can support a maximum bandwidth of 1.6Gbit / S, a dual-byte bus (16 bits) is used inside the module, and the highest frequency ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/05H04L12/26H04L12/40
Inventor 黄科
Owner HUAWEI TECH CO LTD
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