Processor block for forming large-scale extendible processor system

Abstract

A method and system for providing a multiprocessor processor book that is utilized as a building block for a large scale data processing system. Two 4-way multi-chip modules (MCM) are utilized to create the processor book. The first and second MCMs are configured with normal wiring among their respective processors. An additional wiring is provided that links external buses of each chip of the first MCM with buses of a corresponding chip of the second MCM and vice versa. The additional wiring enables each processor of the first MCM substantially direct access to the distributed memory components of the next MCM with no affinity. The processor book is plugged into a processor rack configured to receive multiple processor books that together make up the large scale data processing system.

Description

technical field [0001] The present invention relates generally to data processing systems and, in particular, to multiprocessor data processing systems. More particularly, the present invention relates to a method and system for efficiently interconnecting multiple processors to provide building blocks for large scalable multiprocessor systems. Background technique [0002] The development of commercial data processing systems has advanced rapidly. From the design and use of uniprocessor systems, this development has evolved to the design and use of more complex multiprocessor systems (MP). Most of these developments are driven by industry's growing demand for greater processing power and faster data manipulation. [0003] Technology and commodity servers are two examples of systems that benefit from increased processing power and faster overall data operations. These systems are typically designed with a distributed memory system, with each processor having direct access...

AI Technical Summary

Problems solved by technology

Unfortunately, the small surface area available on a chip to provide buses severely limits the number or overall width of buses, and thus the actual bandwidth that each chip can directly support

[0009] It can be seen that each increase in the number of processors in a processor system becomes increasingly restrictive and increasingly impractical

However, the need for more complex systems with greater numbers of processors still exists

It is very expensive and inefficient to provide a system with above graded switches

[0010] Therefore, several disadvantages of using the above switching topology can be recognized, including: longer memory latency; reduced bandwidth; increased cost due to more wiring and switches, logic and other external components; Increased power requirements and physical space

Images