Splittable multiplier for efficient mixed-precision DSP

A multiplier and multiplication technology, which is applied to calculations using number system representation, instruments, calculations using non-contact manufacturing equipment, etc., can solve problems such as inability to generate correct products

Inactive Publication Date: 2005-01-05
KONINKLIJKE PHILIPS ELECTRONICS NV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, wide operand distributions in two or three two's complement multipliers (such as figure 2 shown in the structure in ) does not produce the correct product

Method used

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  • Splittable multiplier for efficient mixed-precision DSP
  • Splittable multiplier for efficient mixed-precision DSP
  • Splittable multiplier for efficient mixed-precision DSP

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Embodiment Construction

[0016] Detailed Description of Preferred Embodiments

[0017] This invention discusses methods for implementing partitioned two's complement multipliers to provide an efficient degree of subword parallelism for multiplication resources. As an example, it is hoped that the configuration of the double multiplier can be realized as figure 1 Two parallel operations of lower precision shown. And hopefully those same multipliers can support a full precision operation like figure 2 shown in .

[0018] For the VSB DFE example discussed above, three 4x16 multiplier arrays can provide 3 simultaneous multiplications, or one 12x16 multiplication. Therefore, this split multiplier is an important tool for implementing resource and power efficient shared hardware programmable resources.

[0019] The split multiplier implementation will be discussed below for the case of two separate two's complement multipliers. refer to figure 1 , two m-by-p two's complement multipliers 101 and 102 ...

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Abstract

A method and architecture with which to achieve efficient sub-word parallelism for multiplication resources is presented. In a preferred embodiment, a dual two's complement multiplier is presented, such that an n bit operand B can be split, and each portion of the operand B multiplied with another operand A in parallel. The intermediate products are combined in an adder with a compensation vector to correct any false negative sign on the two's complement sub-product from the multiplier handling the least significant, or lower, p bits of the split operand B, or B[p-1:0], where p=n/2. The compensation vector C is derived from the A and B operands using a simple circuit. The technique is easily extendible to 3 or more parallel multipliers, over which an n bit operand D can be split and multiplied with operand A in parallel. The compensation vector C' is similarly derived from the D and A operands in an analogous manner to the dual two's complement multiplier embodiment.

Description

technical field [0001] The present invention relates to digital signal processors ("DSPs"), and more particularly to optimizing multiplication operations in digital signal processing ASIC implementations. Background of the invention [0002] Programmable digital signal processing systems are notoriously inefficient in terms of resources and power for implementation of algorithms mixed with fixed-point precision of signal processing variables. This inefficiency is due to the need to adapt all shared hardware that operates at different precisions to the maximum precision. In other words, the shared hardware must support the maximum necessary precision. As a result, inefficiencies can result when such hardware is used to perform operations that require less precision. [0003] In fixed ASIC implementations, precision is often minimized in order to improve hardware efficiency. The most common example is a decision feedback equalizer for vestigial sideband applications in digi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/533G06F7/52G06F7/53
CPCG06F2207/3828G06F2207/382G06F7/5324G06F7/52
Inventor G·F·布尔恩斯
Owner KONINKLIJKE PHILIPS ELECTRONICS NV
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