Time delay computing method, timing analytic method, approximating method for calculating object network and delay control method

Abstract

A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.

Description

[0001] technology area [0002] The present invention relates to a delay calculation method, a timing analysis method, and a calculation target network for increasing the overall delay time in a fabricated semiconductor device or increasing the speed of arbitrary wiring, which are used in a CAD device for assisting in the design of a semiconductor device, etc. Approximation method and delay control method. Background technique [0003] In recent years, due to the miniaturization of semiconductor processing, the capacitance between adjacent wirings has increased compared with the capacitance to the substrate and the gate capacitance. Therefore, delay calculations using CAD devices that take the capacitance between wirings into account have become mainstream. In addition, a method of analyzing the potential variation time of adjacent wirings while maintaining the time range by the static analysis method, and calculating the delay variation due to the capacitance between adjacent...

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Problems solved by technology

[0010] However, due to the increase in the inter-wiring capacitance and the increase in the wiring resistance accompanying the miniaturization of processing, the power supply voltage for reducing power consumption is lowered, and as Figure 30 As shown, the signal migration changes the potential of the adjacent net, and the power supply or zero potential approximation of the adjacent net gradually becomes invalid.

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