MEMS array, manufacturing method thereof, and MEMS device manufacturing method based on the same
A manufacturing method and array technology, applied in semiconductor/solid-state device manufacturing, manufacturing tools, semiconductor devices, etc., can solve the problems of increasing development time, reducing installation area, wiring delay, etc.
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no. 1 Embodiment approach
[0048] Referring to FIGS. 1 to 6 , a program-controlled MEMS array that can be wired arbitrarily according to a first embodiment of the present invention will be described.
[0049] FIG. 1 is a partial cross-sectional view of a MEMS array that can be wired freely in this example, and FIG. 2 shows an overall schematic view of the MEMS array of the present invention. FIG. 3 is a diagram showing an equivalent circuit of the present example of the cross section shown in FIG. 1 .
[0050] As can be seen from the overall schematic view of the MEMS array of Fig. 2, the MEMS array of the present invention that can be connected arbitrarily, utilizes the semiconductor wafer process, for example in 10mm 2 About 300,000 circuit elements that can be connected arbitrarily are integrated on the Si chip, as shown in Figure 3. In this example, in a 10μm square area T, three LCR circuits are arranged to form one circuit.
[0051] The cross-sectional view shown in FIG. 1 is a cross-sectional vi...
no. 2 Embodiment approach
[0076] In the first embodiment, the switches connecting the adjacent elements are constituted by transistors, but in this example, the switches are constituted by electrostatic switches which are mechanical switches. A driving transistor is required to operate an electrostatic switch, but since a mechanical switch has no change in circuit characteristics when turned on and off compared to a transistor switch, it is advantageous when a circuit is composed of a MEMS array.
[0077] FIG. 10 shows a partial cross-sectional view omitting the substrate of the MEMS array of this example. Elements having the same functions as those in the first embodiment are given the same reference numerals.
[0078] FIG. 10 shows the wiring layers M0 to M4 and the passivation layer P on the substrate. In addition, a Cu capping layer C made of Si nitride or the like is provided between layers to prevent the diffusion of copper in the wiring layer into the insulating film to cause device degradation...
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