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Staged locking of two phase locked loops

A phase-locked loop and coding technology, which is applied in the direction of multiplex communication, automatic power control, time division multiplex system, etc., can solve data rate mismatch, data synchronization, and affect users to listen and/or watch feelings and other issues

Inactive Publication Date: 2005-10-05
INTERDIGITAL CE PATENT HLDG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, with some devices, a data rate mismatch between the rate at which the device receives data and the rate at which the device sends data can create data synchronization issues
This data rate mismatch may be evident, for example, when some of the device's data registers fail to maintain the specified data fill states stably
When such a data rate mismatch occurs, the aforementioned data interruptions may also occur intermittently and thus adversely affect the user's listening and / or viewing experience

Method used

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  • Staged locking of two phase locked loops
  • Staged locking of two phase locked loops
  • Staged locking of two phase locked loops

Examples

Experimental program
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Embodiment Construction

[0012] The exemplifications set forth herein illustrate preferred embodiments of the invention, but these exemplifications should not be construed in any way as limiting the scope of the invention.

[0013] Referring now to the accompanying drawings, see specifically figure 1 , which shows a block diagram of a typical environment 100 suitable for implementing the invention. exist figure 1 In the environment 100 includes a computing device such as a personal computer (PC) 10 and a transmitting device such as a wireless transmitter 15 . The wireless transmitter 15 includes a control section such as a flow controller 20 , an encoding section such as an encoder 30 , an RF transmission section such as an RF transmission circuit 40 , and a signal output section such as an antenna 50 . To illustrate, environment 100 includes components that enable audio signals to be transmitted wirelessly. However, those skilled in the art will intuitively recognize that the principles of the pre...

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Abstract

Data synchronization is achieved in devices which transmit and / or receive audio and / or video data through the staged locking of phase locked loops (PLLs). According to an exemplary embodiment, a transmitter (15) includes a serial data source. An encoder (30) provides encoded data and includes a first PLL (34). A controller (20) includes a second PLL (24) which enables generation of a clock signal (WCLK). The controller (20) is coupled between the serial data source and the encoder (30) for providing the clock signal (WCLK) to the encoder (30). The first PLL (34) of the encoder (30) locks to the clock signal (WCLK).

Description

technical field [0001] The present invention relates generally to data synchronization, and more particularly to techniques for achieving data synchronization in devices such as wireless audio transmitters through staged locking of phase locked loops (PLLs). Background technique [0002] Data synchronization is necessary for certain electronic devices, such as devices that transmit and / or receive audio and / or video signals. For example, in the case of devices transmitting audio signals, lack of data synchronization may cause sound interruptions during reproduction, which adversely affects the user's listening experience. Also, in the case of devices transmitting video signals, lack of data synchronization may cause image interruptions during reproduction, which adversely affects the user's viewing experience. [0003] Data synchronization issues in such devices can be attributed to various factors. For example, for some devices, a data rate mismatch between the rate at whi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/04H03L7/06H04J3/00H04J3/06H04L7/02H04L7/033H04L7/08H04N7/173H04N21/242
CPCH04L7/02H04L7/005H04L7/08H03L7/06H03L7/23H04J3/00
Inventor 卡西米尔·J·克劳利
Owner INTERDIGITAL CE PATENT HLDG