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Memory architecture with memory cell groups

A memory cell and memory group technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as increasing cell size, oxidation of AABE plugs, and thinning of barrier layers

Inactive Publication Date: 2005-10-12
INFINEON TECH AG +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This over-etching may cause the barrier layer to become thinner in the region 274 between the capacitances of the capacitor pair
This could compromise the safety of the barrier, resulting in oxidation of the AABE plug 285 located under region 274
Also, conventional techniques for forming capacitors in a series architecture require the bottom electrode to cover the top electrode
This disadvantageously increases the cell size (eg, area penalty)

Method used

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  • Memory architecture with memory cell groups
  • Memory architecture with memory cell groups
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Embodiment Construction

[0013] image 3 A cross-section of memory bank 302 according to one embodiment of the invention is shown. The memory bank includes a plurality of memory cells 305 formed on a semiconductor substrate 310, eg, comprising silicon. Intuitively, the group includes four memory cells 305 . It should be understood that the set may include any number of memory cells (eg, 2, 8, or 16). Preferably, the number of memory cells in the group is an even number. More specifically, the number of memory cells in the group is 2y, where y is an integer greater than or equal to 1. Typically, y is from 2 to 5.

[0014] Each memory cell includes a cell transistor 330 connected to a capacitor 340 . In one embodiment, the transistor is an n-FET. P-FETs or other types of transistors can also be used. Each cell transistor includes a gate and first and second diffusion regions 331 and 332 . In one embodiment, adjacent cell transistors share a common diffusion region. For a cell transistor having ...

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Abstract

An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.

Description

technical field [0001] The present invention relates to memory integrated circuits (ICs). More specifically, the present invention relates to improved ferroelectric memory ICs having a serial memory architecture. Background technique [0002] Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been studied for use in ferroelectric semiconductor memory devices. A ferroelectric material sits between two electrodes to form a ferroelectric capacitor for storing information. Ferroelectric capacitors exploit the hysteretic polarization properties of ferroelectric materials to store information. The logic value stored in the ferroelectric memory cell depends on the polarization direction of the ferroelectric capacitor. In order to change the polarization direction of a capacitor, a voltage higher than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/22H10B20/00H10B69/00
CPCH01L27/11502H01L27/11507G11C11/22H10B53/30H10B53/00
Inventor 安德烈斯·希利格迈克尔·雅各布小崎取托马斯·勒尔主藤进
Owner INFINEON TECH AG