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Multi-height finfets field effect trabsistor

A fin and height technology, applied in the field of fin field effect transistors, to achieve the effect of sacrificing yield and high channel width quantization

Inactive Publication Date: 2006-06-07
AURIGA INNOVATIONS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are significant issues with fabricating thin oxides, as desired, including repeatability and uniformity of fabrication and control of oxide growth rate during the fabrication process.

Method used

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  • Multi-height finfets field effect trabsistor
  • Multi-height finfets field effect trabsistor
  • Multi-height finfets field effect trabsistor

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Experimental program
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Embodiment Construction

[0026] A group of analog-like circuits that are logically such as sense amplifiers, latches, etc. and SRAM cells. Therefore, the performance of different circuits within the chip can be tuned by changing the channel width of one or more FETs within the device. This allows designers to change the performance of different logic circuits where needed on the chip.

[0027] For FinFET structures, the channel width is proportional to the fin height because, in FinFET devices, the channel width is vertical. Since both sides of the fin are exposed to but insulated from the gate, the channel width is effectively twice the area created by the fin height (multiplied by the fin length). Thus, by increasing or decreasing the fin height (for a given fin length), the channel width (the channel surface area exposed but insulated from the gate) is correspondingly increased or decreased. The present invention provides a method to fabricate FinFETs with different fin heights (channel widths) ...

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PUM

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Abstract

The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2 / 3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

Description

technical field [0001] This invention relates to field effect transistors, and more particularly to fin field effect transistors and to such structures having fins of different heights. Background technique [0002] Since integrated circuits ("ICs") were first created and fabricated in the 1960's, the number and density of devices formed on IC substrates has increased dramatically. In fact, Very Large Scale Integration ("VLSI") devices with more than 100,000 devices on a single chip are generally considered an obsolete technology. In today's market, the fabrication of ICs with hundreds of millions of devices on a single chip is standard technology. IC development with billions of devices per chip is currently underway. Accordingly, the current description of IC fabrication is Very Large Scale Integration ("ULSI"). [0003] As part of the number of devices formed on an IC substrate increases and the device density grows at the same time, the size of the devices decreases s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L21/336H01L21/84H01L27/12H01L29/04H01L29/772H01L29/786
CPCH01L21/84H01L27/1203H01L29/045H01L29/66795H01L29/785H01L21/18
Inventor B·A·雷尼E·J·诺瓦克I·阿勒J·凯纳特T·卢德维格
Owner AURIGA INNOVATIONS INC
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