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Synchronous frequency dividers and components therefor

A technology of frequency divider and synchronous latch, which is applied to synchronous pulse counters, electrical components, pulse counters, etc., and can solve problems such as increased circuit complexity

Inactive Publication Date: 2006-08-16
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the complexity of the circuitry used to generate parallel carries (like carry lookahead) increases exponentially with the number of bits

Method used

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  • Synchronous frequency dividers and components therefor
  • Synchronous frequency dividers and components therefor
  • Synchronous frequency dividers and components therefor

Examples

Experimental program
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Effect test

Embodiment Construction

[0061] Figure 1 to Figure 3 has been described above.

[0062] Figure 4 A master / slave latch is shown consisting of multiple simple latches. This simple latch stores data D (clock CLK is high) or outputs it directly to output Q (CLK is low). Because of the latter function, this simple latch is also called a transparent latch.

[0063] In master slave latch, two simple latches are connected in series. The first simple latch 60 is called the master latch; the second latch 62 is called the slave latch. The slave latch is operated by the inverted clock of the master latch. exist Figure 4 and hereinafter, the inverted signal is shown by the prefix X.

[0064] The master-slave latch inputs data D, which is present on a low-to-high transition of the clock. Similarly, the slave latch becomes transparent when CLK goes from high to low. Therefore, the output changes only on the falling edge of CLK.

[0065] Figure 5 Two master-slave latches are shown, arranged essentially...

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Abstract

A photodetector (1) converts an optical signal in the form of a burst into an electrical signal and outputs an output current, and a preamplifier (2) having a feedback resistive element (2B) amplifies the output current and outputs a voltage signal. The feedback resistive element (2B), a series circuit of a first resistive element (6) and a first switching element (9), and a series circuit of a second resistive element (7) and a second switching element (10) are connected in parallel to a gain varying circuit (3) for varying the conversion gain of the preamplifier (2). The gain varying circuit (3) generates an operation signal to close the first switching element 9 during a first gain varying period and an operation signal to close the second switching element (10) during a second gain varying period.

Description

technical field [0001] The present invention relates to components for synchronous frequency dividers based on half adders, and to synchronous frequency dividers based on half adders. Background technique [0002] A digital frequency divider, also known as a modulo-k counter, is used to generate an output pulse for every K input pulses. Depending on the application, it is desirable to have a wide programming range, for example a programming range of 10 to 127, which requires an N=7 bit counter. [0003] Because of the high-speed operations required, the design must be of the synchronous type, ie, transitions are only allowed on the falling or rising edge of the input signal. In a conventional frequency divider, there are two sources for critical delay. [0004] One source of delay is the need to compare two N-bit numbers simultaneously to detect the end of the count cycle. If the counter is reset / counted to K type, complex logic of N exclusive-or (XOR) gates followed by N...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/66H03K3/2885H03K23/50
CPCH03K23/665H03K3/2885H03K23/50
Inventor 巴尔多·米勒
Owner FUJITSU LTD