Round-grade packing integrated-circuit method
A wafer-level packaging and integrated circuit technology, applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of expensive, time-consuming chips, and achieve the effect of reducing time and cost
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[0015] The present invention includes wafer-level packaging of integrated circuits, and methods of manufacturing wafer-level packaged integrated circuits and their components. Wafer-level packaged integrated circuits are manufactured by bonding a semiconductor lid wafer to the integrated circuit wafer before dicing the integrated circuit wafer, ie, before breaking the integrated circuit into many small chips. A lid wafer covers some or all of the chips on the IC wafer, and the lid wafer is then mechanically bonded to the IC wafer. For example, the two wafers can be bonded to each other by solder at different inverse locations on the lid wafer and each chip near the corresponding location on the integrated circuit wafer. Each die is hermetically sealed between the lid wafer and the integrated circuit wafer to prevent water vapor penetration. The sealing can be achieved by mechanical bonding between the lid wafer and the integrated circuit wafer, or the sealing and mechanical b...
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