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Round-grade packing integrated-circuit method

A wafer-level packaging and integrated circuit technology, applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of expensive, time-consuming chips, and achieve the effect of reducing time and cost

Inactive Publication Date: 2006-10-25
MEMSIC SEMICON WUXI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, after the chips are diced, packaging these individual chips (the "back-end" process of integrated circuit manufacturing) is time-consuming and expensive because each chip must be individually packaged (i.e. serially)

Method used

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  • Round-grade packing integrated-circuit method
  • Round-grade packing integrated-circuit method
  • Round-grade packing integrated-circuit method

Examples

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Embodiment Construction

[0015] The present invention includes wafer-level packaging of integrated circuits, and methods of manufacturing wafer-level packaged integrated circuits and their components. Wafer-level packaged integrated circuits are manufactured by bonding a semiconductor lid wafer to the integrated circuit wafer before dicing the integrated circuit wafer, ie, before breaking the integrated circuit into many small chips. A lid wafer covers some or all of the chips on the IC wafer, and the lid wafer is then mechanically bonded to the IC wafer. For example, the two wafers can be bonded to each other by solder at different inverse locations on the lid wafer and each chip near the corresponding location on the integrated circuit wafer. Each die is hermetically sealed between the lid wafer and the integrated circuit wafer to prevent water vapor penetration. The sealing can be achieved by mechanical bonding between the lid wafer and the integrated circuit wafer, or the sealing and mechanical b...

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PUM

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Abstract

This invention relates to a round chip packaged IC, which is manufactured by pasting round cover chips onto the front of the IC chips before cutting, in which, the round cover chips are pasted mechanically and connected to the IC chips then the chips are cracked, the conduction path extends between the contact welding block on the cover top and the contact points of the IC chips by the round cover chips and the round chip of the cover includes one or many chips, the IC round chip can be manufactured different from that of the cover so as to form a packed mixed round chip level and the top layer cover chips can be laminated to a multi-layer IC.

Description

technical field [0001] The invention relates to the packaging technology of integrated circuits, in particular to the wafer-level packaging technology of integrated circuits. Integrated circuits (ICs) are manufactured from silicon wafers, each containing many individual circuits (chips). After processing is complete, the wafer is cut ("broken") into individual chips. Each chip is then encapsulated in plastic or ceramic, or bonded to a ceramic lid. Background technique [0002] Each chip includes a number of pads for electrical connections. In the package, each pad is bonded to a corresponding pin or other external structure. In one conventional form, wire bonds are used to bond each pad to the corresponding pin. Pins or other structures are used to electrically connect a completed integrated circuit to a circuit board or similar through a soldering process. These solder bonds are also usually the only mechanical bonds between the integrated circuit and the circuit board...

Claims

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Application Information

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IPC IPC(8): H01L21/60
Inventor 赵阳
Owner MEMSIC SEMICON WUXI