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Buffer circuit

A buffer circuit and power supply circuit technology, applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, reliability improvement and modification, etc., can solve the operation speed limit, PMOS transistor signal rising slowly, semiconductor Increased device size, etc.

Inactive Publication Date: 2006-11-01
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Furthermore, in order to reduce the parasitic resistance of the transistor, the transfer gate 1204 must have a larger transistor size, which results in an increase in the size of the semiconductor device
Moreover, the signal rise of the PMOS transistor P1 is slow due to the parasitic resistance of the transfer gate 1204 transistor, which results in a limitation on the operating speed

Method used

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no. 1 example

[0028] figure 1 A buffer circuit 100 according to a first embodiment of the present invention is shown. Refer below figure 1 The buffer circuit 100 will be specifically described. The buffer circuit 100 uses one input / output (I / O) terminal in an input mode and an output mode. The I / O terminal of the buffer circuit is connected to, for example, an I / O terminal of a semiconductor device. The buffer circuit includes an output buffer 101 used in an output mode and an input buffer 102 used in an input mode. The output buffer 101 outputs a signal DATA, which is supplied from an internal circuit to an I / O terminal, during an output mode. The input buffer 102 outputs the signal input to the input / output circuit to the internal circuit. The output mode and the input mode are switched by the OEB signal input to the buffer circuit 100 from the internal circuit. If the OEB signal is at a low level (such as ground voltage GND), the buffer circuit 100 enters an output mode; if the OEB...

no. 2 example

[0078] Image 6 is a circuit diagram of a buffer circuit 600 according to a second embodiment of the present invention. The buffer circuit 600 of the second embodiment is basically the same circuit as the buffer circuit 100 of the first embodiment. The buffer circuit 600 of the second embodiment differs from the buffer circuit 100 of the first embodiment in the connection of the gate of the PMOS transistor P10 in the N-well controller 116 . The same elements as those of the buffer circuit 100 of the first embodiment are denoted by the same reference numerals and will not be described in detail here.

[0079] The gate of the PMOS transistor P10 in the buffer circuit 100 of the first embodiment is connected to the I / O terminal. In the buffer circuit 600 of the second embodiment, the gate of the PMOS transistor P10 is connected to a line connecting the NMOS transistor N7 and the PMOS transistor P9 of the power supply circuit 114 .

[0080] In this connection, the N-well contro...

no. 3 example

[0086] Figure 9 is a circuit diagram of a buffer circuit 900 according to a third embodiment of the present invention. The buffer circuit 900 of the third embodiment is basically the same circuit as the buffer circuit 100 of the first embodiment. The buffer circuit 900 of the third embodiment differs from the buffer circuit 100 of the first embodiment only in that the PMOS transistor P7 is omitted. The same elements as those of the buffer circuit 100 of the first embodiment are denoted by the same reference numerals and will not be described in detail here.

[0087] The buffer circuit 900 of the third embodiment does not have the PMOS transistor P7. However, when an external power supply voltage is input to the I / O terminal, the external power supply voltage is supplied to the gate of the PMOS transistor P9 through the NMOS transistor N8 and the PMOS transistor P8. Therefore, since the connection between the pre-driver 111 and the power supply voltage VDD is blocked, curre...

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PUM

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Abstract

A buffer circuit capable of switching between input mode and output mode includes a first transistor for outputting a prescribed voltage to an input / output terminal depending on a conductive state during the output mode of the buffer circuit, a pre-driver for controlling the conductive state of the first transistor during the output mode of the buffer circuit, and a power supply circuit for providing a first power supply to the pre-driver during the output mode of the buffer circuit and providing or blocking the first power supply to the pre-driver in accordance with an input voltage to the input / output terminal during the input mode of the buffer circuit.

Description

field of invention [0001] The present invention relates to a snubber circuit, and more particularly to a snubber circuit that does not allow current to flow into a terminal even when a voltage higher than a power supply voltage is input from the outside of the terminal. Background technique [0002] Recent semiconductor devices have various functions and use various input / output signals. At the same time, semiconductor devices are required to have as few terminals as possible. Recently, the method adopted to meet this requirement is to use one terminal in input mode and output mode. However, in order to reduce power consumption, recent technologies operate semiconductor devices and semiconductor devices mounted in electronic equipment by using a plurality of power supply systems corresponding to their functions, such as a 3.3V power supply system and a 5.0V power supply system, thereby operating the entire electronic equipment. In this electronic device, when a signal is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0175H03K19/0185
CPCH03K19/00315
Inventor 砂入崇二
Owner RENESAS ELECTRONICS CORP
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