Nonvolatile semicondutor storage device and manufacturing method thereof
A non-volatile, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as the shape that hinders the stability of the control gate, hinders the size of the groove, and increases the area of the memory cell
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no. 1 example
[0025] A first exemplary embodiment of the present invention will be described below with reference to FIGS. 1 and 2F. FIG. 1 shows the structure of one memory cell in the nonvolatile semiconductor memory of this embodiment. FIG. 2F shows the structure of the nonvolatile semiconductor memory of this embodiment. As shown in FIG. 1, the memory cell 100 in the nonvolatile semiconductor memory of the present embodiment includes a semiconductor substrate 101, a drain 102, a groove (referred to as a trench) 103, a source 104, a first gate Insulating film 105 , floating gate 106 , second gate insulating film 107 , control gate 108 , and offset region 109 . This embodiment uses a floating gate as an example of a storage node described in the claims for demonstration purposes.
[0026] The drain 102 is formed on the surface of the semiconductor substrate 101 . The semiconductor substrate 101 has a groove 103 inside which a source electrode 104 is formed on the bottom surface. The f...
no. 2 example
[0041] Hereinafter, referring to FIG. 3, a second exemplary embodiment of the present invention will be described. FIG. 3 is a cross-sectional view showing the structure of one memory cell in the nonvolatile semiconductor memory according to the present embodiment. In FIG. 3, the same elements as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 3, in the nonvolatile semiconductor memory of this embodiment, a storage unit 100 in a storage unit includes a semiconductor substrate 101, a drain 102, a groove 103, a source 104, a first gate insulating film 105 , floating gate 106 , second gate insulating film 107 , control gate 108 , offset region 109 , first insulating film 110 a , first insulating film 110 b , and semiconductor film 114 . In the first embodiment, the groove 103 is formed directly in the semiconductor substrate 101, whereas in the present embodiment, the groove 103 is formed in the first insulating film 110a. Therefore, the semiconduct...
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