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Arithmetic operation unit, information processing apparatus and arithmetic operation method

A technology of arithmetic operation unit and information processing equipment, applied in the direction of electrical digital data processing, digital data processing components, calculation, etc., can solve the problem of increased delay, prevent the increase of delay, increase the clock frequency, and reduce hardware resources Effect

Inactive Publication Date: 2007-06-06
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0035] However, when method (1) is adopted, the delay becomes larger

Method used

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  • Arithmetic operation unit, information processing apparatus and arithmetic operation method
  • Arithmetic operation unit, information processing apparatus and arithmetic operation method
  • Arithmetic operation unit, information processing apparatus and arithmetic operation method

Examples

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Embodiment Construction

[0066] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0067] [1] Embodiment of the present invention in the case of single-precision arithmetic

[0068]First, the structure of the floating-point multiply-adder according to the embodiment of the present invention will be described with reference to the block diagram shown in FIG. 1 . Incidentally, like reference numerals in the drawings designate like or corresponding components, and thus their detailed descriptions are partially omitted here.

[0069] As shown in Figure 1, the floating-point multiplication adder 1 includes a right shifter (straightener) 10, a multiplier [CSA (carry-save adder) tree] 11, a CSA (carry-save adder) 12, an absolute value adder Adder (Abs. Adder) 13, Shift Quantity Calculator [L.Z. (Leading Zero) Predictor] 20, Normalizer (Left Shifter) 30, Rounder 40, and Sticky Bit Generator 50.

[0070] The floating-point multiply-adder 1 suppo...

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PUM

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Abstract

An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit outputting the arithmetic operation result, a normalizer having a plurality of shifter normalizing the arithmetic operation result, a shift amount calculator calculating a plurality of shift amounts for the plural shifter, and a predictor generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator generating the information by using the interim information. The cycle time required to generate a sticky bit is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit is reduced.

Description

technical field [0001] The present invention relates to a technique for rounding the result of an arithmetic operation by using a sticky bit in a floating-point multiply-adder (FMA) in an arithmetic operation unit. More specifically, the present invention relates to techniques for efficiently obtaining sticky bits when using predictive theory, wherein predictive theory determines that within an error range of a predetermined bit (for example, a "1" bit) to use in the rounding process of the result of an arithmetic operation The normalized shift amount of . Background technique [0002] The floating-point multiply-adder (FMA) used here is configured as shown in FIG. 12, for example. The floating-point multiply-adder 100 shown in FIG. 12 includes a right shifter (aligner (aligner)) 10, a multiplier [CSA (carry-save adder) tree] 11, a CSA (carry-save adder) 12, an absolute A value adder (Abs. adder) 13 , a shift amount calculator [L.Z. (Leading Zero) predictor] 20 , a normali...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/302
CPCG06F7/483G06F7/49952G06F7/74G06F7/5443G06F7/49957G06F5/012G06F2207/382G06F7/00
Inventor 田尻邦彦
Owner FUJITSU LTD