Semiconductor device having a recessed gate structure and method of manufacturing the same

Abstract

A method of forming a semiconductor device on a substrate comprising the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

Description

[0001] 1. Field of the Invention[0002] This invention relates generally to the field of semiconductor device fabrication and more specifically to the fabrication of a semiconductor device having a recessed gate.[0003] 2. Background of the Invention[0004] As integrated circuit technology advances and integrated circuit device dimensions decreases, it has become increasingly common to employ trench isolation methods to form trench isolation regions between active regions of a semiconductor device. Such trench isolation methods may employ chemical mechanical polishing (CMP) to provide a nominally planarized surface for an isolation trench that has been filled with an insulator. Typically, a CMP planarization of a wafer involves holding the wafer against a rotating polishing pad that is subjected to a silica-based alkaline slurry. The polishing pad also applies pressure against the wafer.[0005] While it is desirable to use CMP planarization during the fabrication of semiconductor device...

AI Technical Summary

Benefits of technology

[0011] By reducing the number of CMP steps, the present invention further permits a reduction in cost and in processing time. The invention can also avoid or reduce CMP step problems that lead to defective devices, loss of device yield, and lack of device reliability.

[0012] The invention also advantageously provides a gate surface that is substantially at the same level as the surfaces of the source / drain regions, thereby facilitating the formation of electrical connections during the contact etching and formation process.

[0013] The invention also advantageously provides a structure that permits the source / drain regions to be doped at a sufficient level so as to reduce the fusion impurities that degrade the transistor characteristics.

Problems solved by technology

While it is desirable to use CMP planarization during the fabrication of semiconductor devices, the CMP planarization step may present some problems and drawbacks.

For example, each additional CMP step leads to additional costs and additional processing time in the semiconductor fabrication process.

Additionally, a CMP step on a newly formed layer on the wafer may cause alignment targets thereon to lose their steps after the CMP method is performed.

All of the above results may contribute to defective devices, loss of device yield, and lack of device reliability.

This additional CMP step can lead to the problems mentioned above.

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