Method of manufacturing a cylindrical storage node in a semiconductor device
a semiconductor device and storage node technology, applied in semiconductor devices, capacitors, electrical devices, etc., can solve the problems of reducing the reliability of the final semiconductor device, generating bridge defects, and unable to maintain sufficient capacitance in the semiconductor memory devi
Inactive Publication Date: 2002-05-02
SAMSUNG ELECTRONICS CO LTD
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Problems solved by technology
The center area of the cell is then etched more than the cell surrounding areas by an amount of about 3000 .ANG. so that the height of the cylindrical node becomes lower than before, which renders maintaining sufficient capacitances in the semiconductor memory device difficult.
As a result, defects such as bridge defects are generated as the next process steps are performed on the wafer.
Such defects may lead to failure in driving the semiconductor device, such as twin-bit failure in electrical die sorting EDS tests, which decreases the reliability of the final semiconductor devices.
However, the CMP process changes the surface morphology of a wafer and produces non-uniform heights of the storage nodes between cells or chips because of micro scratches, which also result in lowering device reliability.
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[0021] Korean Patent Application No. 2000-63415, filed on Oct. 27, 2000, and entitled: "Cylindrical Storage Node Manufacturing Method in Semiconductor Device", is incorporated herein by reference in its entirety.
[0022] The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those of ordinary skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, and one or more intervening layers may also be pres...
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A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.
Description
[0001] 1. Field of the Invention[0002] The present invention refers to a method of manufacturing a cylindrical storage node in a semiconductor device with a minimum loss difference of a conductive layer between the center and the edge of cell areas during an etch-back process of storage node isolation. The method of manufacturing a cylindrical storage node according to the present invention maintains electric capacitance uniformity over the entire cell area of a wafer and results in improved device reliability.[0003] 2. Description of the Related Art[0004] A semiconductor memory device like a dynamic random access memory (DRAM) includes cell capacitors for storing data. As the degree of integration in a semiconductor memory device increases, the area of a cell unit decreases. Therefore, several approaches to guarantee availability of required capacitances in a limited space of a semiconductor memory device are researched and developed.[0005] In general, cylindrical stack structures ...
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IPC IPC(8): H01L21/302H01L21/02H01L21/3065H01L21/321H10B12/00
CPCH01L21/3212Y10S438/949H01L28/91H10B12/00
Inventor CHOI, SUNG-GILAHN, TAE HYUKJEONG, SANG SUPCHUNG, DAE HYUKLEE, WON JUN
Owner SAMSUNG ELECTRONICS CO LTD