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Memory read circuitry

a read circuit and memory technology, applied in the field of data processing systems, can solve the problems of slow performance, large register file size, additional time required to charge and discharge this extra capacitance,

Inactive Publication Date: 2003-01-23
ORACLE INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the register file can be quite large.
As a result, additional time is required to charge and discharge this extra capacitance.
Such additional time equates to increased read and write times and hence, slower performance.
In addition to wasting power and generating heat, this crowbar current can also result in electro-migration related reliability issues.
Even though the read circuit shown in FIG. 2 eliminates the crowbar current, the read circuit is not optimal.

Method used

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Embodiment Construction

[0024] The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0025] 5.1 Improved Read Circuit

[0026] FIG. 3 presents an improved read circuit 300. The read circuit 300 includes a precharge input 301. The read circuit 300 also includes a first switch 302. In this embodiment, the first switch is a PMOS transistor. The gate of the first switch is coupled to the precharge input 301. The source of the first s...

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Abstract

A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Description

1. FIELD OF THE INVENTION[0001] The present invention generally relates to data processing systems. More specifically, the present invention relates to memory systems, precharge circuitry and read circuitry.2. BACKGROUND[0002] As technology advances, memories in semiconductor devices have become larger and more advanced. The number of memory cells on Dynamic Random Access Memories is ever increasing. In addition, modern microprocessors utilize register files that include a large number of registers. Such register files may include multiple read and write access ports. As a result, the register file can be quite large.[0003] A semiconductor memory typically includes a memory cell array that has a grid of bitlines and wordlines, with memory cells located at intersections of the bitlines and the wordlines. During operation, the bitlines and the wordlines are selectively asserted and negated to enable at least one of the memory cells to be read or written.[0004] Increasing demands for l...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C7/12
CPCG11C7/12
Inventor DESAI, SHAISHAV A.TAWARI, DEVENDRA N.
Owner ORACLE INT CORP