Digital fractional phase detector

Abstract

A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.

Description

BACKGROUND OF INVENTION [0001] 1. Field of the Invention [0002] The invention relates to a digital fractional phase detector, and more particularly, to a digital fractional phase detector for use in a digital frequency synthesizer. [0003] 2. Description of the Prior Art [0004] Frequency synthesizers using analog circuit techniques are well known in the art. Conventional RF frequency synthesizer architectures are analog-intensive and generally require a low loop bandwidth to reduce the familiar and well-known reference or compare frequency spurs. [0005] The conventional PLL-based frequency synthesizers generally comprise analog-intensive circuitry that does not work very well in a low voltage constrained high-speed CMOS environment. Such frequency synthesizers do not take advantage of recently developed high-density digital gate technology. [0006] Newer frequency synthesizer architectures have used sigma-delta modulated frequency divider techniques to randomize the above discussed fr...

AI Technical Summary

Benefits of technology

[0011] It is an advantage of the present invention digital fraction phase detector that no over-sampling clock is needed.

[0012] It is a further advantage of the claimed invention digital fractional phase detector that the quantizer directly measures the pulse width of the phase error signal output from the phase error detector.

[0013] These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

Problems solved by technology

Conventional RF frequency synthesizer architectures are analog-intensive and generally require a low loop bandwidth to reduce the familiar and well-known reference or compare frequency spurs.

The conventional PLL-based frequency synthesizers generally comprise analog-intensive circuitry that does not work very well in a low voltage constrained high-speed CMOS environment.

Such frequency synthesizers do not take advantage of recently developed high-density digital gate technology.

Such architectures cannot be used at RF frequencies.

However, because the VCO output clock and the reference clock are not synchronous signals with respect to each other, quantization resolution and accuracy is not optimal.

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