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Semiconductor device and wire bonding apparatus

a technology of semiconductor devices and wire bonding devices, which is applied in the direction of electrical devices, semiconductor devices, and semiconductor/solid-state device details, etc., can solve the problems of shortening the internal circuit of the chip, difficult to improve the efficiency of semiconductor device development, etc., and achieves a high degree of design freedom and high efficiency

Inactive Publication Date: 2005-02-10
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a semiconductor device that allows for flexibility in designing its internal circuit layout and efficient development. The semiconductor device includes a chip, bonding pads, and inner leads connected by bonding wires. The bonding wires have bends electrically isolated from conductive parts on the chip, and the bonding pads can be placed at optional positions on the chip surface. The wire bonding apparatus used for fabricating this semiconductor device sets ratios between the distance between the bonding pad and the bend in the bonding wire to the overall length of the wire, and forms the bends at positions corresponding to the ratios. This invention allows for efficient and flexible semiconductor device design."

Problems solved by technology

Therefore, it has been difficult to improve the efficiency of developing semiconductor devices greatly.
More specifically, it is possible that the internal circuit of the chip is shorted if the bonding wire touches the chip.

Method used

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  • Semiconductor device and wire bonding apparatus
  • Semiconductor device and wire bonding apparatus
  • Semiconductor device and wire bonding apparatus

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Effect test

first embodiment

[0027] First Embodiment

[0028] Hereinafter, a first embodiment according to the present invention will be described in detail with reference to FIG. 1. FIG. 1 is a schematic view of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device includes a die pad 1, a chip 2 provided with an internal circuit and mounted on the die pad 1, a surface (major surface) 2a of the chip 2, a bonding pad 3 formed on the surface 2a of the chip 2, a surface 3a of the bonding pad 3, an inner lead 4 disposed opposite to the bonding pad 3, a surface 4a of the inner lead 4, a bonding wire (metal loop) 5 electrically interconnecting the bonding pad 3 and the inner lead 4, bends K1 to K4 in the bonding wire 5.

[0029] Actually, the semiconductor device has a plurality of bonding pads 3, a plurality of inner leads 4 and a plurality of bonding wires 5, only one of the bonding pads 3, one of the inner leads 4 and one of the bonding wires 5 ...

second embodiment

[0040] Second Embodiment

[0041] Hereinafter, a second embodiment according to the present invention will be described with reference to FIG. 2. FIG. 2 is a schematic view of a semiconductor device according to the second embodiment of the present invention. The semiconductor device in the second embodiment differs from the semiconductor device in the first embodiment in the arrangement of the nearest bend K4 to the inner lead 4.

[0042] Referring to FIG. 2, the semiconductor device includes a die pad 1, a chip 2, a bonding pad 3, an inner lead 4, a bonding wire 5, and bends K1 to K4 formed in the bonding wire 5.

[0043] The bends K1 to K4, similarly to those of the bonding wire 5 of the first embodiment, are formed in that order from the side of the bonding pad 3. The nearest bend K4 to the inner lead 4 is at a level higher than that of the nearest bend K1 to the chip 2; that is, the height of the bend K4 from the surface 2a of the chip 2 is higher than the height H of the nearest bend...

third embodiment

[0048] Third Embodiment

[0049] Hereinafter, a third embodiment according to the present invention will be described with reference to FIG. 3. FIG. 3 is a schematic view of a semiconductor device according to the third embodiment of the present invention. The present embodiment differs from the semiconductor devices in the first and the second embodiment in the position of one (bend K2) of a plurality of bends (bends K1 to K4) in each of bonding wires.

[0050] Referring to FIG. 3, there is shown the semiconductor device including a die pad 1, a chip 2, an electrically insulating part 2al in a surface 2a of the chip 2, a bonding pad 3, an inner lead 4, a bonding wire 5, and bends K1 to K4 formed in the bonding wire 5.

[0051] The bends K1 to K4, similarly to those of the bonding wire 5 of the foregoing embodiment, are formed in that order from the side of the bonding pad 3. The bend K2 is in contact with the electrically insulating part 2al of the chip 2. The electrically insulating part...

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PUM

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Abstract

A semiconductor device comprises a chip; a plurality of bonding pads provided on the chip; and a plurality of inner leads arranged opposite to the bonding pads. Further the semiconductor device comprises a plurality of bonding wires electrically connecting the bonding pads and the corresponding inner leads, respectively. Each of the bonding wires has a plurality of bends electrically isolated from conductive parts on the chip, and the bonding pads are arranged at optional positions on a surface of the chip. Hence the shorting of the chip by the bonding wires can be reliably prevented, the bonding wire having a high mechanical strength can be stably fed, the bonding pads may be optionally arranged on the chip, the degree of freedom of designing the layout of the internal circuit of the chip is high, and the semiconductor device and the wire bonding apparatus can be developed at a high efficiency.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a wire bonding apparatus and, more particularly, to a semiconductor device fabricated by interconnecting inner leads and bonding pads formed on a surface of a chip at a level above that of the surfaces of the inner leads, and a wire bonding apparatus for use for fabricating such a semiconductor device. [0003] 2. Background Art [0004] There has been demand for producing inexpensive, stable semiconductor devices by enhancing the efficiency of development of chips for fabricating semiconductor devices. [0005] A chip included in a semiconductor device is provided internally with an integrated circuit, and a plurality of bonding pads formed on a surface of the chip. Electric signals are exchanged through the bonding pads between the internal integrated circuit of the chip and an external circuit. [0006] When fabricating a semiconductor device, a chip provided wi...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/60H01L23/28H01L23/495
CPCH01L23/4952H01L2924/00014H01L24/48H01L24/85H01L2224/05556H01L2224/05599H01L2224/4809H01L2224/48095H01L2224/48247H01L2224/484H01L2224/85148H01L2224/85399H01L2924/01004H01L2924/01005H01L2924/01013H01L2924/01082H01L2924/14H01L24/05H01L2924/01033H01L2224/04042H01L2924/01037H01L2224/78H01L2224/45099H01L2924/00H01L2224/05554
Inventor HORIBE, HIROSHI
Owner RENESAS TECH CORP