Semiconductor device and wire bonding apparatus
a technology of semiconductor devices and wire bonding devices, which is applied in the direction of electrical devices, semiconductor devices, and semiconductor/solid-state device details, etc., can solve the problems of shortening the internal circuit of the chip, difficult to improve the efficiency of semiconductor device development, etc., and achieves a high degree of design freedom and high efficiency
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first embodiment
[0027] First Embodiment
[0028] Hereinafter, a first embodiment according to the present invention will be described in detail with reference to FIG. 1. FIG. 1 is a schematic view of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device includes a die pad 1, a chip 2 provided with an internal circuit and mounted on the die pad 1, a surface (major surface) 2a of the chip 2, a bonding pad 3 formed on the surface 2a of the chip 2, a surface 3a of the bonding pad 3, an inner lead 4 disposed opposite to the bonding pad 3, a surface 4a of the inner lead 4, a bonding wire (metal loop) 5 electrically interconnecting the bonding pad 3 and the inner lead 4, bends K1 to K4 in the bonding wire 5.
[0029] Actually, the semiconductor device has a plurality of bonding pads 3, a plurality of inner leads 4 and a plurality of bonding wires 5, only one of the bonding pads 3, one of the inner leads 4 and one of the bonding wires 5 ...
second embodiment
[0040] Second Embodiment
[0041] Hereinafter, a second embodiment according to the present invention will be described with reference to FIG. 2. FIG. 2 is a schematic view of a semiconductor device according to the second embodiment of the present invention. The semiconductor device in the second embodiment differs from the semiconductor device in the first embodiment in the arrangement of the nearest bend K4 to the inner lead 4.
[0042] Referring to FIG. 2, the semiconductor device includes a die pad 1, a chip 2, a bonding pad 3, an inner lead 4, a bonding wire 5, and bends K1 to K4 formed in the bonding wire 5.
[0043] The bends K1 to K4, similarly to those of the bonding wire 5 of the first embodiment, are formed in that order from the side of the bonding pad 3. The nearest bend K4 to the inner lead 4 is at a level higher than that of the nearest bend K1 to the chip 2; that is, the height of the bend K4 from the surface 2a of the chip 2 is higher than the height H of the nearest bend...
third embodiment
[0048] Third Embodiment
[0049] Hereinafter, a third embodiment according to the present invention will be described with reference to FIG. 3. FIG. 3 is a schematic view of a semiconductor device according to the third embodiment of the present invention. The present embodiment differs from the semiconductor devices in the first and the second embodiment in the position of one (bend K2) of a plurality of bends (bends K1 to K4) in each of bonding wires.
[0050] Referring to FIG. 3, there is shown the semiconductor device including a die pad 1, a chip 2, an electrically insulating part 2al in a surface 2a of the chip 2, a bonding pad 3, an inner lead 4, a bonding wire 5, and bends K1 to K4 formed in the bonding wire 5.
[0051] The bends K1 to K4, similarly to those of the bonding wire 5 of the foregoing embodiment, are formed in that order from the side of the bonding pad 3. The bend K2 is in contact with the electrically insulating part 2al of the chip 2. The electrically insulating part...
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