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Manufacturing method of semiconductor-on-insulator region structures

Inactive Publication Date: 2005-04-21
STMICROELECTRONICS SRL +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012] The present invention aims at providing a method of manufacturing a transistor struc

Problems solved by technology

However, this is only a compromise between two opposite constraints.

Method used

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  • Manufacturing method of semiconductor-on-insulator region structures
  • Manufacturing method of semiconductor-on-insulator region structures
  • Manufacturing method of semiconductor-on-insulator region structures

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Embodiment Construction

[0031] For clarity, the same elements have been referred to with the same reference numerals and further, as usual in the representation of integrated circuits, the various drawings are not to scale.

[0032] A feature of the present invention is to provide single-crystal semiconductor-on-insulator regions intended to receive at least one component, the insulator comprising overthicknesses.

[0033] The present invention will be described, as a non-limiting example, as applied to single-crystal silicon regions of substantially constant thickness (FIGS. 2 and 4A to 4F), and to single-crystal silicon regions comprising overthicknesses. In these last cases, an embodiment in which the overthicknesses of the insulator are under overthicknesses of the silicon region will be considered in relation with FIGS. 3A to 3H and another embodiment in which the overthicknesses of the insulator are under portions of the superposed silicon region comprising no overthickness will be considered in relation...

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Abstract

A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to methods for manufacturing structures of semiconductor regions on insulator. [0003] The present invention is described hereafter in relation with the integration of a MOS transistor. [0004] 2. Discussion of the Related Art [0005]FIG. 1 illustrates, in partial simplified cross-section view, the structure of a MOS transistor formed in a conventional silicon-on-insulator (SOI) region. [0006] The transistor comprises an insulated gate G laid on a portion of a silicon substrate 2 on insulator of a first conductivity type, for example, P. More specifically, the portion of substrate 2 in which the transistor is formed is defined by vertical insulation areas 3 of shallow trench insulation (STI) type. Substrate 2 and trenches 3 rest upon an insulating layer 4 of a uniform thickness T that separates them from a semiconductor wafer 6. Source / drain regions 8 extend, at the surface of substrate 2,...

Claims

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Application Information

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IPC IPC(8): H01L21/762
CPCH01L21/76202H01L21/76251H01L29/78606H01L29/78603H01L29/66772
Inventor MONFRAY, STEPHANEHALIMAOUI, AOMARCORONEL, PHILIPPELENOBLE, DAMIENFENOUILLET-BERANGER, CLAIRE
Owner STMICROELECTRONICS SRL