Electrically Programmable Three-Dimensional Memory Structures and Cells

Abstract

The present invention makes various improvements to the electrically programmable three-dimensional memory (EP-3DM), including its structure and cell design. Redundancy can be employed to improve its yield.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a division of Sr. No. 10 / 615,669, Filed Jul. 8, 2003, which is a division of Sr. No. 10 / 230,648, Filed Aug. 28, 2002, now U.S. Pat. No. 6,717,222. [0002] This patent application relates to the following domestic patent applications: [0003] 1. “3D-ROM-Based IC Test Structure”, provisional application Ser. No. 60 / 328,119, filed on Oct. 7, 2001; [0004] 2. “Three-Dimensional Read-Only Memory Integrated Circuits”, provisional application Ser. No. 60 / 332,893, filed on Nov. 18, 2001; [0005] 3. “Three-Dimensional Read-Only Memory”, provisional application Ser. No. 60 / 354,313, filed on Feb. 1, 2002, and the following foreign patent applications: [0006] 1. “Three-Dimensional-Memory-Based Self-Test Integrated Circuits and Methods”, CHINA P. R., patent application Ser. No. 02113586.X, filed on Apr. 8, 2002; [0007] 2. “Three-dimensional Memory System-on-a-Chip”, CHINA P.R., patent application Ser. No. 02113738.2, filed on May 15...

AI Technical Summary

Benefits of technology

"The present invention provides a three-dimensional integrated memory (3D-M) that can be easily integrated with other components on a substrate, such as processors and analog blocks. The 3D-M is formed by integrating a memory cell layer with a substrate circuit. The substrate circuit includes a plurality of gaps between certain address-select lines, which help to pass through wires and provide interface for the substrate circuit. The 3D-M is also designed with a simple cell structure and a large capacity, which minimizes the impact of the peripheral circuits on the layout of the substrate circuit. The invention also provides a method for self-aligning the 3D-ROM layer with the word and bit lines, which simplifies the manufacturing process and improves the integratibility of the 3D-M."

Problems solved by technology

Because logic and analog blocks are sensitive to defects and non-single-crystalline semiconductor material has a large defect density, the 3D-IC comprising logic and / or analog blocks have a low yield.

Moreover, logic and / or analog blocks consume large power.

The three-dimension integration of these blocks faces many heat-dissipation issues.

Moreover, it consumes little power.

However, because it is typically based on non-single-crystalline semiconductor, the performance of the 3D-M cell cannot yet compete with the conventional memory.

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