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High polarization ferroelectric capacitors for integrated circuits

a high-polarization, ferroelectric capacitor technology, applied in the direction of capacitors, semiconductor devices, electrical apparatus, etc., can solve the problems of destructive read operation, achieve high switching polarization, facilitate ferroelectric switching properties, and avoid read operation

Inactive Publication Date: 2005-07-07
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention relates to a method and structure for manufacturing integrated circuits with ferroelectric memory cells. The method involves heating the substrate and subjecting it to a temperature program to induce stresses on the ferroelectric cores, which causes a switched polarization of the cores. This results in a higher switched polarization of the memory cells, allowing them to be made smaller and more densely packed. The structure includes metal plugs that add to the thermal stresses that reorient the domains during cooling. The technical effects of the invention include improved performance and reliability of the ferroelectric memory cells.

Problems solved by technology

A characteristic of the illustrated ferroelectric memory cell is that if the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value after the cell is read.

Method used

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  • High polarization ferroelectric capacitors for integrated circuits
  • High polarization ferroelectric capacitors for integrated circuits
  • High polarization ferroelectric capacitors for integrated circuits

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Embodiment Construction

[0021] The present invention will now be described with reference to the accompanying drawings in which like numbered elements represent like parts. The present invention can be used to fabricate stand-alone FeRAM devices or FeRAM devices integrated into a semiconductor chip that has many other device types.

[0022]FIG. 3 provides a schematic illustrating how stresses are applied according to the present invention to reorient the domains of a ferroelectric core 60. A stack 58 comprising the ferroelectric core 60, a material 62 above the ferroelectric core 60 and a material 64 below the ferroelectric core 60. The materials are stacked in the z-direction. One of, and preferably both of, the materials 62 and 64, have a larger coefficient of thermal expansion (CTE) than the ferroelectric core 60. As the materials are cooled below the temperatures at which they were formed, the materials 62 and 64 shrink faster than the ferroelectric core 60 and, through shear stresses, exert a compressiv...

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Abstract

One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.

Description

FIELD OF THE INVENTION [0001] The present invention relates generally to the field of integrated circuit manufacturing, and more particularly relates to ferroelectric RAM. BACKGROUND OF THE INVENTION [0002] Ferroelectric memory, and other types of semiconductor memory, are used for storing data and / or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the second bitline being connected to a reference voltage...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/02H10B20/00H10B69/00
CPCH01L27/11502H01L28/55H01L27/11507H10B53/30H10B53/00
Inventor MOISE, THEODORE S. IVSUMMERFELT, SCOTT R.UDAYAKUMAR, K.R.
Owner TEXAS INSTR INC
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