Evaluation of a temporal description within a general purpose programming language

a general purpose programming language and temporal description technology, applied in the field of hardware functional verification, can solve the problems that the ordinal execution mechanism provided by general purpose programming language compilers cannot handle such a situation, and the language syntax cannot be easily changed to support hardware simulation

Inactive Publication Date: 2006-12-07
JEDA TECHNOLOGIES
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Benefits of technology

[0009] The above need is met by a translation module that translates a temporal description into a temporal expression. The translation module is adapted to translate a temporal description in the form of an extended syntax or a preprocessing macro to the temporal expression. The temporal expression includes a native expression of a general purpose programming language. The temporal expression may also include one or more construct functions. A parsing module generates a data structure that represents the temporal expression without evaluating the native expression. Particularly, the parsing module is adapted to parse the temporal expression to generate the data structure. During the parse phase, the parsing module creates a data structure, copies a return address in a stack to a data structure for future evaluation. Then it avoids evaluating the native expression during the parse phase by controlling a construct function's return value to be

Problems solved by technology

In a general purpose programming language, however, the language syntax cannot be easily changed to support hardware simulation.
H

Method used

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  • Evaluation of a temporal description within a general purpose programming language
  • Evaluation of a temporal description within a general purpose programming language
  • Evaluation of a temporal description within a general purpose programming language

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Embodiment Construction

[0020]FIG. 1 is a high-level block diagram of a computing environment 100 according to an embodiment of the present invention. FIG. 1 illustrates that the computing environment 100 includes a transformation module 102 (generally referred to as a translation module), a preprocessing module 104 (also generally referred to as a translation module), and an execution module 106. Those of skill in the art will understand that other embodiments of the computing environment 100 can have different and / or other modules than the ones described herein. In addition, the functionalities can be distributed among the modules in a manner different than described herein.

[0021] In an embodiment of the invention, a temporal description is written within a general purpose programming language such as C++. The temporal description can be expressed with either an extended syntax or a preprocessor macro. In the case of an extended syntax, the transformation module 102 (e.g., a parser program or a compiler...

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Abstract

A translation module translates a temporal description into a temporal expression. The translation module is adapted to translate a temporal description in the form of an extended syntax or a preprocessing macro to the temporal expression. The temporal expression includes a native expression of a general purpose programming language. The temporal expression may also include one or more construct functions. A parsing module parses the temporal expression to generate a data structure that represents the temporal expression without evaluating the native expression. An evaluation module evaluates the data structure to execute the temporal expression including the native expression.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention pertains in general to hardware functional verification and in particular to techniques for evaluating a temporal description within a general purpose programming language. [0003] 2. Background Art [0004] Using a temporal description to verify a hardware design is increasingly common. Hardware description languages such as the problem statement language (PSL) are becoming standards to verify hardware designs and various electronic design automation (EDA) tools are beginning to support the evaluation of such a temporal description. For example, a hardware description language such as System Verilog uses the temporal description mechanism to check the correctness of a hardware behavior during hardware simulation. Special purpose programming languages developed for designing hardware can adopt such a new language construct (i.e., temporal description) with an additional syntax. [0005] Another trend of ha...

Claims

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F8/427G06F17/504G06F8/43G06F30/3323
Inventor KASUYA, ATSUSHI
Owner JEDA TECHNOLOGIES
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