Method for producing a memory with high coupling ratio

Abstract

A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.

Description

RELATED APPLICATIONS [0001] The present application is based on, and claims priority from, Taiwan Application Serial Number 94130391, filed Sep. 5, 2005, the disclosure of which is hereby incorporated by reference herein in its entirety.BACKGROUND [0002] 1. Field of Invention [0003] The present invention relates to a method for producing a memory. More particularly, the present invention relates to a method for producing a memory with high coupling ratio. [0004] 2. Description of Related Art [0005] Memory-related technology is progressing rapidly. Because of the high market demand for lighter, thinner and smaller products, flash memory is extensively used and has become a main nonvolatile memory nowadays. Because the physical size of the memory is becoming smaller and smaller, the size of each memory cell within the memory structures also must be made smaller, which results in decreasing the overlapping area of a floating gate and a control gate in each memory cell. Therefore, the c...

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Benefits of technology

[0009] It is therefore an aspect of the present invention to provide a method for producing a memory. The memory has high coupling ratio, the memory thus can read and write data faster.

[0010] Another aspect of the present invention relates to a method for producing a memory structure, wherein a concave portion is not formed on the edge of shallow trench isolation during wet etching process, and thus electric leakage is reduced.

[0012] Since the spacer protects the edge of the shallow trench isolation from being etched and from being concave portiond in the etching process, electric leakage does not occur when the memory is functioning. Furthermore, the fact that the top of the spacer is higher than the surface of the shallow trench isolation results in a curvature on the surface of the floating gate when the floating gate is formed on the substrate. The surface area of the floating gate is therefore increased, which allows a greater overlapping area between the floating gate and the control gate and increases the coupling ratio of the memory structure. Accordingly, the memory of the present invention can function more efficiently and is more reliable.

Problems solved by technology

Moreover, the conventional memory has a serious parasitic transistor effect that is described in detail below.

The presence of the polysilicon in the concave portion 109 causes difficulties in performing the subsequent etching process.

Furthermore, there is likely an electric leakage in the region of the concave portion 109, which adversely effects the operation and reliability of the memory.

Furthermore, the fact that the top of the spacer is higher than the surface of the shallow trench isolation results in a curvature on the surface of the floating gate when the floating gate is formed on the substrate.

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