30results about How to "Threshold voltage uniform" patented technology

In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.

In semiconductor devices and methods of manufacturing semiconductor devices, a zirconium source having zirconium, carbon and nitrogen is provided onto a substrate to form an adsorption layer of the zirconium source on the substrate. A first purging process is performed to remove a non-adsorbed portion of the zirconium source. An oxidizing gas is provided onto the adsorption layer to form an oxidized adsorption layer of the zirconium source on the substrate. A second purging process is performed to remove a non-reacted portion of the oxidizing gas. A nitriding gas is provided on the oxidized adsorption layer to form a zirconium carbo-oxynitride layer on the substrate, and a third purging process is provided to remove a non-reacted portion of the nitriding gas.

The invention provides a method for manufacturing a transistor. The method comprises the steps of providing a substrate, wherein a false gate structure is formed on the substrate, the false gate structure comprises a gate dielectric layer, a protective layer located on the gate dielectric layer, an oxide layer located on the protective layer and a false gate located on the oxide layer, the gate dielectric layer is made of oxygen containing materials, and oxygen diffuses to the upper surface of the protective layer, so that an oxidation layer is formed; forming the source electrode and the drain electrode of the transistor after the false gate structure is formed; forming an interlayer dielectric layer on the substrate after the source electrode and the drain electrode are formed, wherein the upper surface of the false gate structure is exposed through the interlayer dielectric layer; eliminating the false gate, wherein a false gate trench is formed in the interlayer dielectric layer; eliminating the oxide layer and the oxidation layer after the false gate trench is formed; forming a gate electrode in the false gate trench after the oxide layer and the oxidation layer are eliminated. By the adoption of the method for manufacturing the transistor, the transistor can obtain an even threshold voltage, and therefore the performance of the transistor is improved.

The invention discloses a process method for improving the cell density of a trench MOSFET and a trench MOSFET structure. The method comprises the following steps: depositing polycrystalline silicon,removing the polycrystalline silicon outside a trench, removing first silicon nitride, forming a first doped region and a third doped region in an epitaxial layer, depositing second silicon nitride, etching the second silicon nitride, and forming side walls on the side walls of the polycrystalline silicon, wherein the widths of the side walls formed by the left side wall and the right side wall ofthe polycrystalline silicon are equal; injecting boron atoms or phosphorus atoms into the first doped region to form a second doped region, wherein the doping concentration of the second doped regionis 20-100 times that of the first doped region, removing the side walls, removing polycrystalline silicon protruding out of the surface of the first oxide layer, depositing a dielectric layer, removing the dielectric layer and silicon in a set region, and forming source region contact holes. The process method for improving the cell density of the trench MOSFET and the trench MOSFET structure provided by the invention have the advantages of being capable of realizing more uniform threshold voltage and conduction resistance and the like.

Disclosed is a 3D memory device comprising a substrate; a stacked structure on the substrate and including a plurality of conductor layers and a plurality of insulating layers alternately stacked; a plurality of memory strings extending through the stacked structure; a plurality of conductive channels extending through the stacked structure; wherein the plurality of memory strings are configured as a honeycomb structure; each of the conductive channels is located at the center of the honeycomb structure and is configured to supply power to a plurality of memory strings around the substrate through the substrate. The present invention also provides a method for fabricating a 3D memory device provided by the present invention. The method, by using a common-source hole as a deposition channel to replace a sacrificial layer in the stacked structure with a conductor layer and using the common-source hole to form a common-source conductive channel, avoids voids between the conductor layersand the common-source conductive channel in the gate stacked structure.

A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.