30results about How to "Threshold voltage uniform" patented technology

A power-on reset circuit includes a Schmitt trigger circuit, a voltage divider, and a compensate circuit. The Schmitt trigger circuit includes a plurality of MOS devices of a uniform threshold voltage (Vt) for determining a power reset trigger level. The voltage divider is coupled to an input of the Schmitt trigger circuit for tracking the supply signal. The compensate circuit is operative to generate a small reset pulse to compensate for temperature and the supply signal variation effect.

A method for fabricating a nonvolatile memory device includes forming a gate insulation layer, a first gate conductive layer, a first sacrificial layer, and a second sacrificial layer over a substrate, etching the first and second sacrificial layers, the first gate conductive layer, the gate insulation layer, and the substrate to form trenches, forming a first insulation layer to fill the trenches, polishing the first insulation layer using the etched second sacrificial layer as a polish stop layer, removing the second sacrificial layer, recessing the first insulation layer inside the trenches, forming a second insulation layer to fill a space produced inside the trenches by the recessing of the first insulation layer, and polishing the second insulation layer using the etched first sacrificial layer as a polish stop layer.

In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.

The invention discloses a semiconductor structure. The semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction which is perpendicular to the first direction and the second direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers of the channel layers is greater than the space in the third direction between the two uppermost channel layers of the channel layers in the same semiconductor stack. This makes it possible to obtain a more uniform threshold voltage of a nanosheet transistor comprising channel layers in each semiconductor stack.

The disclosure provides a storage device, a recessed channel array transistor and a preparation method thereof, belonging to the technical field of storage. The preparation method of the recessed channel array transistor includes: forming a substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked in sequence; implanting the first ion into the first semiconductor layer; implanting the first ion into the second semiconductor layer The second ion of the same type as the first ion, and the implantation dose is greater than the second ion; forming a groove channel opening in the third semiconductor layer and extending to the first semiconductor layer; implanting through the bottom of the groove channel and the first ion type The opposite third ion; the difference between the implantation dose of the first ion and the second ion is less than the implantation dose of the third ion; forming a gate insulating layer and a gate; implanting in the third semiconductor layer is opposite to the second ion type of the fourth ion. The preparation method of the recessed channel array transistor can improve the uniformity of the threshold voltage of the recessed channel array transistor.

In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions are etched to form trenches for isolation in the respective isolation regions. The trenches for isolation are filled with an insulating layer to form isolation layers in the respective trenches. A lower passivation layer is formed over an entire surface including top surfaces of the isolation layers. A first oxide layer is formed over an entire surface including the lower passivation layer. Meta-stable bond structures within the lower passivation layer are removed. A nitride layer, a second oxide layer, and an upper passivation layer are sequentially formed over an entire surface including the first oxide layer.

Disclosed is a 3D memory device, comprising: a substrate; a stacked structure on the substrate, the stacked structure including a plurality of conductor layers and a plurality of insulating layers stacked alternately; a plurality of memory strings running through the The stacked structure; a plurality of conductive channels running through the stacked structure; wherein, the plurality of storage strings are in a honeycomb structure, and each of the conductive channels is located at the center of the honeycomb structure and is used to pass through the substrate and supplying power to the plurality of storage strings around it. The present invention also provides a manufacturing method of the 3D memory device provided by the present invention, using the common source hole as a deposition channel to replace the sacrificial layer in the laminated structure with a conductor layer, and using the common source hole to form a common source conductive channel, avoiding the formation of gaps between the conductor layer in the gate stack structure and the common-source conductive channel.

The invention provides a method for manufacturing a transistor. The method comprises the steps of providing a substrate, wherein a false gate structure is formed on the substrate, the false gate structure comprises a gate dielectric layer, a protective layer located on the gate dielectric layer, an oxide layer located on the protective layer and a false gate located on the oxide layer, the gate dielectric layer is made of oxygen containing materials, and oxygen diffuses to the upper surface of the protective layer, so that an oxidation layer is formed; forming the source electrode and the drain electrode of the transistor after the false gate structure is formed; forming an interlayer dielectric layer on the substrate after the source electrode and the drain electrode are formed, wherein the upper surface of the false gate structure is exposed through the interlayer dielectric layer; eliminating the false gate, wherein a false gate trench is formed in the interlayer dielectric layer; eliminating the oxide layer and the oxidation layer after the false gate trench is formed; forming a gate electrode in the false gate trench after the oxide layer and the oxidation layer are eliminated. By the adoption of the method for manufacturing the transistor, the transistor can obtain an even threshold voltage, and therefore the performance of the transistor is improved.

The invention relates to a semiconductor device, a preparation method thereof, and an electronic device. The preparation method comprises: providing a semiconductor substrate including a central region and an edge region, wherein a plurality of floating gate structures are formed in the semiconductor substrate and shallow trench isolation structures are formed between the adjacent floating gate structures and downwardly extend to the semiconductor substrate; removing a part of oxide in the shallow trench isolation structures by using etching back in order to form a groove and expose a part of the sidewalls of the floating gate structures; depositing a covering layer in order to fill the groove and cover the floating gate structures; and removing a part of the covering layer by using wet etching in order to expose a part of the sidewalls of the floating gate structures again. The method further deposits the covering layer after a COPEN processing step, then removes the covering layer by using wet etching, and leaves a part of the covering layer at the edge region in order to compensate the thickness of the oxide in the edge area, thereby improving device performance and yield.

In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions are etched to form trenches for isolation in the respective isolation regions. The trenches for isolation are filled with an insulating layer to form isolation layers in the respective trenches. A lower passivation layer is formed over an entire surface including top surfaces of the isolation layers. A first oxide layer is formed over an entire surface including the lower passivation layer. Meta-stable bond structures within the lower passivation layer are changed to stable bonds. A nitride layer, a second oxide layer, and an upper passivation layer are sequentially formed over an entire surface including the first oxide layer.

The disclosure relates to a method for manufacturing an array substrate, the array substrate, a display panel and a display device. The manufacturing method includes: providing a substrate, the substrate includes a first region and a second region; forming a light-shielding layer on the first region; forming a buffer layer covering the light-shielding layer and the substrate; The first active layer and the second active layer, the first active layer corresponds to the first region, and the second active layer corresponds to the second region; the first gate insulation is formed on the surface of the first active layer away from the substrate layer and the first gate stacked on the first gate insulating layer, and a second gate insulating layer and a second gate stacked on the second gate insulating layer are formed on the surface of the second active layer away from the substrate; the first gate The orthographic projection of the pole is located in the first gate insulating layer, and the orthographic projection of the second gate is located in the second gate insulating layer; the distance between the edge of the first gate and the edge of the first gate insulating layer is greater than the edge of the second gate The spacing from the edge of the second gate insulating layer.

A transistor and a forming method thereof are disclosed. The forming method of the transistor comprises the following steps: providing a substrate with a pseudo gate film on the surface; etching part of the pseudo gate film in the thickness direction; after etching part of the pseudo gate film in the thickness direction, forming a second initial pseudo gate layer and a plurality of first initial pseudo gate layers on the surface of the second initial pseudo gate layer, wherein a first opening is formed between every two adjacent second initial pseudo gate layers; oxidizing the sidewalls of the first initial pseudo gate layers and the second initial pseudo gate layer on the bottoms of the first openings, forming a first oxide layer on the sidewall surfaces of the first initial pseudo gate layers, and making the second initial pseudo gate layer on the bottoms of the first openings form a second oxide layer and the remaining second initial pseudo gate layer and first initial pseudo gate layers form pseudo gates, wherein the bottom size of the pseudo gates is greater than the top size; forming a dielectric layer on the surface of substrate, wherein the dielectric layer exposes the top surfaces of the pseudo gates; removing the pseudo gates, and forming second openings in the dielectric layer; and forming gate structures in the second openings. The performance of the formed transistor is improved.