Transistors and methods of forming them

A technology of transistors and dummy gate layers, applied in the field of transistors and their formation, can solve problems such as poor performance and poor morphology of high-K gate metal gate transistors, and achieve the effect of balanced threshold voltage and stable performance

Active Publication Date: 2018-12-21
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the high-K metal-gate transistors formed by the gate-last process have poor morphology and poor performance

Method used

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  • Transistors and methods of forming them
  • Transistors and methods of forming them
  • Transistors and methods of forming them

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] As mentioned in the background art, the high-K metal gate transistor formed by the gate-last process has poor appearance and poor performance.

[0036] For details, please refer to Figure 1 to Figure 3 , Figure 1 to Figure 3 It is a schematic cross-sectional structure diagram of a process of forming a high-K metal gate transistor by a gate-later process according to an embodiment of the present invention.

[0037] Please refer to figure 1 , providing a substrate 100, the surface of the substrate 100 has a dummy gate layer 101; a dielectric layer 102 is formed on the surface of the substrate 100, the dielectric layer 102 covers the sidewall of the dummy gate layer 101, and the dielectric Layer 102 exposes the top surface of the dummy gate layer 101 .

[0038] Please refer to figure 2 , removing the dummy gate layer 101 (such as figure 1 As shown), an opening 103 is formed in the dielectric layer 102 .

[0039] Please refer to image 3 , forming a gate dielectri...

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PUM

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Abstract

A transistor and a forming method thereof are disclosed. The forming method of the transistor comprises the following steps: providing a substrate with a pseudo gate film on the surface; etching part of the pseudo gate film in the thickness direction; after etching part of the pseudo gate film in the thickness direction, forming a second initial pseudo gate layer and a plurality of first initial pseudo gate layers on the surface of the second initial pseudo gate layer, wherein a first opening is formed between every two adjacent second initial pseudo gate layers; oxidizing the sidewalls of the first initial pseudo gate layers and the second initial pseudo gate layer on the bottoms of the first openings, forming a first oxide layer on the sidewall surfaces of the first initial pseudo gate layers, and making the second initial pseudo gate layer on the bottoms of the first openings form a second oxide layer and the remaining second initial pseudo gate layer and first initial pseudo gate layers form pseudo gates, wherein the bottom size of the pseudo gates is greater than the top size; forming a dielectric layer on the surface of substrate, wherein the dielectric layer exposes the top surfaces of the pseudo gates; removing the pseudo gates, and forming second openings in the dielectric layer; and forming gate structures in the second openings. The performance of the formed transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, is continuously reduced to meet the miniaturization and development of integrated circuits. Integration requirements, and transistor devices are one of the important components of MOS devices. [0003] For transistor devices, as the size of the transistor continues to shrink, the gate dielectric layer formed of silicon oxide or silicon oxynitride material in the prior art cannot meet the performance requirements of the transistor. In particular, transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer are prone to a series of problems such as leaka...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/336H01L29/423H01L29/78
Inventor 赵杰
Owner SEMICON MFG INT (SHANGHAI) CORP
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