Auto precharge circuit sharing a write auto precharge signal generating unit

Abstract

In the auto precharge circuit, a plurality of read auto precharge signal generating units and a plurality of auto precharge signal output units share a single write auto precharge signal generating unit. Each read auto precharge signal generating unit logically combines an internal CAS command signal, an internal address signal and a pre auto precharge signal to generate an auto precharge detect signal and a read auto precharge signal. The write auto precharge signal generating unit delays the read auto precharge signal by a predetermined time to generate a write auto precharge signal. Each auto precharge signal output unit logically combines the internal CAS command signal, an internal address signal, a read auto precharge signal, and a write auto precharge signal to output an auto precharge signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority to Korean patent application number 2007-0081811 filed on Aug. 14, 2007, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of reducing the area occupied by an auto precharge circuit.[0003]In a typical semiconductor memory device, the word line is automatically disabled upon completion of a write operation in response to a write command that includes an auto precharge command. The disabling is performed by an auto precharge control circuit included within the semiconductor memory device. When the write command, which includes the auto precharge command, is inputted to the semiconductor memory device, the auto precharge control circuit automatically generates the precharge signal at a predetermined time point after the input operation o...

AI Technical Summary

Benefits of technology

The present invention provides an auto precharge circuit that minimizes circuit area by sharing a write auto precharge signal generating unit among auto precharge blocks. The circuit includes multiple read auto precharge signal generating units, each of which logically combines an internal CAS command signal, an internal address signal, and a pre auto precharge signal to generate an auto precharge detect signal and a read auto precharge signal. A write auto precharge signal generating unit delays any one of the read auto precharge signals by a predetermined time to generate a write auto precharge signal. The read and write auto precharge signals are then combined by multiple auto precharge signal output units to output an auto precharge signal. The use of a single write auto precharge signal generating unit among multiple banks reduces the total area of the semiconductor device and improves cell efficiency.

Problems solved by technology

The write auto precharge signal generating unit 30 shown in FIG. 1 must be formed in each bank even though each write auto precharge signal geneawrting unit 30 has the same structure, resulting in the area of the semiconductor device being unnecessarily large.

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