Method and system for global coverage analysis

Abstract

Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application is a divisional of U.S. patent application Ser. No. 11 / 454,075, filed on May 31, 2006, which is a continuation-in-part of U.S. Pat. No. 7,216,318, filed on Apr. 29, 2004, entitled “A METHOD AND SYSTEM FOR FALSE PATH ANALYSIS” which claims priority to U.S. Provisional Application Ser. No. 60 / 466,698, filed on Apr. 29, 2003, all of which are hereby incorporated by reference in their entirety.BACKGROUND AND SUMMARY[0002]Static timing analysis (STA) can determine if there exist paths in an electrical circuit design with delays that exceed a given timing threshold. Such paths are commonly known as critical paths (CPs). When such a critical path is identified, the portion of the design associated with the critical path may need to be modified to satisfy the required timing thresholds. It is generally not preferred to make such design modifications if they can be avoided, since each such modification consumes time and sys...

AI Technical Summary

Benefits of technology

[0013]Embodiments of the present invention provide a method and system for performing automatic STA coverage analysis while existing constraints can be automatically verified and/or automatically regenerated to ensure complete STA coverage. Using some emb

Problems solved by technology

It is generally not preferred to make such design modifications if they can be avoided, since each such modification consumes time and system resources, as well as possibly introducing less optimal component configurations and sizes.

However, mismanagement of the sets of constraints and corresponding STA runs could cause less than 100% STA coverage resulting in undetected critical paths.

Typically, the constraints for each mode are created and analyzed manually Generation of constraints for each mode and subsequent STA analysis for a typical design can take several weeks to several months and is very error prone and complete coverage is not easy to determine.

However, design changes may cause some of the constraints to become invalid.

The constraints that are manually generated initially might not he re-verified when incremental changes are made to the design.

The constraints that are no longer valid (invalid constraints) can cause incomplete STA coverage and a bad design to be implemented.

For example, some static timing tools detect paths that are logically never used, with Automated test Pattern Generation (ATPG) techniques; however, these techniques have been limited to a single set of constraints or single mode of operation without consideration, of additional constraints or modes that can be imposed by independent STA r

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