Semiconductor storage device and method of controlling semiconductor storage device

a semiconductor storage device and storage device technology, applied in the direction of memory address/allocation/relocation, instruments, computing, etc., can solve the problems of inefficient parallel processing of the chips, etc., to prevent deterioration in write/read performance of the device, reduce the time each chip is in an idle state, and prevent performance deterioration

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a semiconductor storage device and storage device technology, applied in the direction of memory address/allocation/relocation, instruments, computing, etc., can solve the problems of inefficient parallel processing of the chips, etc., to prevent deterioration in write/read performance of the device, reduce the time each chip is in an idle state, and prevent performance deterioration

US20090070520A1Active Publication Date: 2009-03-12HITACHI LTD

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[0033]An embodiment of the present invention will be described with reference to the accompanying drawings.

[0034]FIG. 1 is a diagram briefly showing an internal configuration for a semiconductor storage device 1000 that utilizes the invention. The semiconductor storage device 1000 is composed of a host interface 1010, a memory controller 1020, a host data buffer 1030, a temporary data buffer 1040, and plural (e.g., 16) flash memory chips 1100 to 1115.

[0035]The host interface 1010 is an interface mechanism connected to an external host(s) (not shown in the drawing), and transmits data stored in the flash memory chips 1100 to 1115 to the host and receives write data to be stored in the flash memory chips 1100 to 1115 from the host in response to read / write request commands from the host.

[0036]Incidentally, the host specifies a logical storage position for the data requested to be subject to read / write by using a logical address (hereinafter referred to as “LBA (Logical Block Address)”...

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Abstract

In a semiconductor storage device, a memory controller divides each of blocks in each of chips into a first page set composed of pages and a second page set composed of pages, divides a logical address space into groups, and divides each group into lines. Block units are created each of which is obtained by assembling a predetermined number of blocks from the blocks in each chip. A predetermined number of block units from the block units are managed as standard block units, and the other block units are managed as spare block units. Each standard block unit is made to correspond to one group. The corresponding group data is stored in the pages in the first page set in each block constituting the standard block unit, and unwritten pages for recording update data for the group data are provided to be included in the second page set.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application relates to and claims priority from Japanese Patent Application No. 2007-231640, filed on Sep. 6, 2007, the entire disclosure of which is incorporated herein by reference.BACKGROUND[0002]1. Field of the Invention[0003]The invention relates to a semiconductor storage device and a method of controlling the semiconductor storage device, and is particularly suitable for use in a semiconductor storage device using an electrically rewritable non-volatile memory as a storage medium and a method of controlling the semiconductor storage device.[0004]2. Description of Related Art[0005]A semiconductor storage device in which data in a logical block is distributed to plural flash memory physical blocks to be stored, and when the data stored in each of the physical blocks is updated, the relevant update data is recorded in a blank page in the physical block, and the original stored data is invalidated; and in which, if the physical b...

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Application Information

Patent Timeline

12 Mar 2009

Publication

US20090070520A1

IPC: G06F12/02

CPC: G06F2212/7208; G06F12/0246

Inventors: MIZUSHIMA, NAGAMASA