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Semiconductor device

a technology of semiconductor devices and semiconductors, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of increasing package size, difficult to reduce inductance, and easy deformation and damage of wires (bonding wires)

Inactive Publication Date: 2010-08-12
TOSHIBA MEMORY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is a semiconductor device that includes a semiconductor chip with electrodes, a bed portion, leads, a hanging pin, bus bars, a rectifying bus bar, and bonding wires. The semiconductor chip is mounted on the bed portion and connected to the leads, bus bars, and rectifying bus bar through the bonding wires. The resin sealed body seals the semiconductor chip, bed portion, bus bars, and bonding wires. The technical effect of this invention is to provide a semiconductor device with improved performance and reliability.

Problems solved by technology

However, the increase in the number of external terminals leads to a problem of increasing the package size.
However, in the semiconductor device in such a structure, wires (bonding wires) have been susceptible to deformation and damage due to non-uniformity in arrangement of the common leads in a molding process of a resin sealed body.
Further, the leads have not always been optimally arranged, causing a problem of difficulty in reducing the inductance.

Method used

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  • Semiconductor device
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Examples

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Embodiment Construction

[0013]Hereinafter, embodiments for implementing the present invention will be described. Note that the embodiments will be described with reference to the drawings in the following description, but those drawings are provided merely for graphic illustration, and the present invention is not limited to those drawings.

[0014]FIG. 1A and FIG. 1B are longitudinal sectional views showing a first embodiment of a semiconductor device according to the present invention, and FIG. 2 is a plan view showing a shape of a frame (lead frame) used in the semiconductor device of the first embodiment. Note that the semiconductor device of the first embodiment will be described taking a QFP as an example, but the semiconductor device of the present invention is not limited to the QFP.

[0015]The semiconductor device (QFP) 10 of the first embodiment includes a frame (a lead frame) 1 having a shape illustrated below, a semiconductor chip 2 mounted on a bed portion (a stage portion) 11 of the frame 1, bondi...

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Abstract

This semiconductor device has a frame including a bed portion on which a semiconductor chip is mounted, lead groups arranged in an outer peripheral portion, first bus bars, second bus bars and a rectifying bus bar. The first bus bars and the second bus bars are arranged between the bed portion and the lead groups. The rectifying bus bar is arranged in a region where the second bus bar is not arranged. Wire bonding is not performed on the rectifying bus bar. The rectifying bus bar includes a third bus bar having at least one end joined to a lead or a hanging pin and / or a fourth bus bar formed by extending the first bus bar in an outer peripheral direction in which the leads are arranged. The semiconductor device is provided in which deformation and damage of bonding wires when molding a resin sealed body are prevented.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-28942, filed on Feb. 10, 2009; the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]Conventionally, to cope with an increase in the number of signals due to enhancement of the function of LSI, semiconductor devices of the QFP (Quad Flat Package) type are being developed. In the semiconductor device of the QFP type, since wire bonding is implemented between inner leads of a lead frame and electrodes of a semiconductor chip on a basis of one-to-one correspondence, the number of terminals that can be drawn from the semiconductor chip to the outside of the package is substantially equal to the number of inner leads, that is, the number of external terminals (pins) of the package. Therefore, in a semiconductor device incorporating a semiconductor chip requiring a number of electrode...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/50H01L23/495H01L23/31
CPCH01L2924/01006H01L24/48H01L2924/30107H01L2924/01082H01L2924/01079H01L2224/32245H01L2224/48253H01L23/3107H01L23/49503H01L23/4952H01L23/49541H01L23/49551H01L24/45H01L24/49H01L2224/45144H01L2224/48091H01L2224/48247H01L2224/48465H01L2224/49109H01L2224/49171H01L2224/73265H01L2924/01004H01L2924/01033H01L2924/01047H01L2924/00014H01L2924/00H01L2924/181H01L2924/00012
Inventor TSUMORI, TAKU
Owner TOSHIBA MEMORY CORP