Generating parallel simd code for an arbitrary target architecture

Abstract

Techniques are disclosed for automating the generation of parallel SIMD native source code in three major functional areas of data transmission, synchronization, and SIMD operations. An annotation standard is defined that is independent from native compilers and, coupled with a source-to-source compiler that provides high-level abstractions of data transmission, synchronization, and SIMD operations, relieves the need for programmers to work in a hardware-specific manner, while addressing issues of productivity and portability in a parallel SIMD computing environment.

Description

FIELD OF THE INVENTION[0001]Embodiments of the invention generally relate to compilers. More specifically, embodiments of the invention relate to techniques for automating the generation of parallel SIMD native source code for an arbitrary target architecture.DESCRIPTION OF THE RELATED ART[0002]Many modern processors support single instruction, multiple data (SIMD) extensions. SIMD indicates a single instruction that operates on a number of data items in parallel. For example, an “add” SIMD instruction may add eight 16 bit values in parallel. These instructions increase execution speed dramatically by accomplishing multiple operations within one instruction. Examples of SIMD instructions include multimedia extension (“MMX”) instructions, SSE instructions, and vectored multimedia extension (“VMX”) instructions.[0003]While computer hardware has supported multiple forms of parallelism for many years, it is well-recognized that programmers are not always able to use these performance fe...

AI Technical Summary

Benefits of technology

The invention provides a method for generating source code for a parallel computing architecture. This involves receiving annotated source code that specifies the target architecture and the one or more parallel application operations to be performed on that architecture. The source code is then parsed and translated into a form that can be executed on the target architecture. This allows for the efficient and effective development of parallel applications that can be executed on a range of architectures.

Problems solved by technology

While computer hardware has supported multiple forms of parallelism for many years, it is well-recognized that programmers are not always able to use these performance features very productively.

This may result from lack of standardization and difficulty in converting non-parallel algorithms to a parallel architecture due to lack of sufficient software abstractions within the programming languages to handle new computing architectures.

The inability of programmers to use these performance features very productively may also result from a lack of support in computer programming languages, as many popular languages were developed before parallelism was widely available (e.g., C, C++) and focus on utilizing a single thread of execution in a single machine.

New languages face acceptance difficulties.

Without a wide user base, a new language (even if designed specifically for portable parallel performance productivity) can easily be less portable, perform more slowly, and impede programmer productivity more than hardware-specific approaches.

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