Semiconductor memory which enables reliable data writing with low supply voltage by improving the conductance via access transistors during write operation

Abstract

A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M00 comprises a pair of inverters cross-coupled with each other, a first switching unit provided between bit line BL and the output terminal of one of the inverters, and a second switching unit provided between bit line XBL and the output terminal of the other inverter. The first switching unit and the second switching unit are controlled to be conductive such that the conductance of the switches be larger for the writing operation than for the reading operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a Divisional of U.S. patent application Ser. No. 11 / 396,511, filed Apr. 4, 2006, which claims the benefit of priority from Japanese Patent Application No. 2005-367150 filed on Dec. 20, 2005. The entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor memory and particularly to a single port static random-access memory (hereinafter also referred to as “SRAM” in a single word).[0004]2. Description of Related Art[0005]As an example, FIG. 14 is a circuit diagram that shows the design of a memory cell in a conventional Static Random Access Memory (SRAM).[0006]This SRAM memory cell M100 shown in FIG. 14 comprises a latch circuit that includes a p-type MOS transistor P101 and an n-type MOS transistor N101, which are connected with each other in series between a supply voltage VCC and a ground voltage VSS, and...

AI Technical Summary

Benefits of technology

[0022]The present invention is to solve the above problem of the prior art by providing a semiconductor memory that maintains securely the contents stored in the memory cells and that enables reliable writing in the memory cells even with a low supply voltage.

[0034]By this, for the writing operation, the conductance of the path between the bit line and the inverter is made larger than that between the output terminal of the inverter and the ground voltage. As a result, the inversion to the low level is achieved easily. For the inverter, the ratio in conductance of the transistors disposed on the supply-voltage side and on the ground-voltage side is determined to set the threshold voltage, at which the output of the inverter is turned over, to an approximately half of the supply voltage. In this way, the semiconductor memory is made reliable for maintaining the contents stored in the memory cells as well as for writing data into the memory cells.

[0045]By this, for the writing operation, the output power on the low level side or the high level side of the latch circuit, which comprises the cross-coupled inverters, becomes comparatively lower. As a result, the level on the side where the output power has decreased is easily turned over. For the inverter, the ratio in conductance of the transistors disposed on the supply-voltage side and on the ground-voltage side is determined to set the threshold voltage, at which the output of the inverter is turned over, to an approximately half of the supply voltage. In this way, the semiconductor memory is made reliable for maintaining the contents stored in the memory cells as well as for writing data into the memory cells.

Problems solved by technology

This presents a possibility that the contents stored in the memory cells may become corrupted.

However, condition n-type MOS transistor N103>p-type MOS transistor P101 in conductance for writing operation may not be satisfied because of the uneven quality of semiconductor memories as products.

If this condition is not satisfied, then it is a problem because the writing operation will not be reliable.

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