Semiconductor memory which enables reliable data writing with low supply voltage by improving the conductance via access transistors during write operation

a technology of access transistor and data writing, which is applied in the field of single-port static random access memory, can solve the problems of inability to meet the conductance of writing operation of mos transistor pb>101/b>, inability to write operation reliable, and content stored in memory cells may become corrupted, etc., and achieve the effect of easy turning over
US20110110146A1Inactive Publication Date: 2011-05-12FUJITSU SEMICON LTD
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
FUJITSU SEMICON LTD
Publication Date
2011-05-12
Estimated Expiration
Not applicable · inactive patent

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Abstract

A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M00 comprises a pair of inverters cross-coupled with each other, a first switching unit provided between bit line BL and the output terminal of one of the inverters, and a second switching unit provided between bit line XBL and the output terminal of the other inverter. The first switching unit and the second switching unit are controlled to be conductive such that the conductance of the switches be larger for the writing operation than for the reading operation.
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Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a Divisional of U.S. patent application Ser. No. 11 / 396,511, filed Apr. 4, 2006, which claims the benefit of priority from Japanese Patent Application No. 2005-367150 filed on Dec. 20, 2005. The entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory and particularly to a single port static random-access memory (hereinafter also referred to as “SRAM” in a single word).

[0004] 2. Description of Related Art

[0005] As an example, FIG. 14 is a circuit diagram that shows the design of a memory cell in a conventional Static Random Access Memory (SRAM).

[0006] This SRAM memory cell M100 shown in FIG. 14 comprises a latch circuit that includes a p-type MOS transistor P101 and an n-type MOS transistor N101, which are connected with each other in series between a supply voltage VCC and a ground voltage VSS, and...

Claims

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