Metal semiconductor alloy structure for low contact resistance

Abstract

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application is a divisional application of U.S. patent application Ser. No. 12 / 849,390 filed on Aug. 3, 2010 the contents of which are incorporated herein by reference.BACKGROUND[0002]The present disclosure relates to metal semiconductor alloy structures for providing low contact resistance and methods of forming the same.[0003]Metal semiconductor alloys such as metal silicides, metal germanides, metal germano-silicides reduce contact resistance between a metal structure such as a metal contact via structure and a semiconductor region such as a source region, a drain region, and a gate conductor line. Formation of metal semiconductor alloys requires an interdiffusion between a metal and a semiconductor material. Typically, the metal is provided as a metal layer, which is deposited after deposition of a dielectric material layer overlying a semiconductor layer and formation of holes within the dielectric material layer to expose the ...

AI Technical Summary

Benefits of technology

The patent describes a semiconductor structure and a method for its formation. The structure includes a trench in a semiconductor material region, a metal semiconductor alloy region, and a contact via structure. The contact via structure includes a lower contact via portion that is located within the metal semiconductor alloy region and laterally and vertically spaced from the semiconductor material region by the metal semiconductor alloy region. The method involves forming at least one dielectric material layer over a semiconductor structure, forming a trench in the dielectric material layer, and forming a metal semiconductor alloy region by diffusing a metal into the semiconductor material region through a sidewall of the trench. The technical effect of this patent is the formation of a semiconductor structure with improved contact between metal and semiconductor materials.

Problems solved by technology

Thus, the volume of the metal semiconductor alloy formed by the anneal is limited by the area of the contact between the metal layer and the underlying semiconductor material.

However, a high contact resistance of a metal semiconductor alloy region adversely impacts device performance by introducing extra parasitic resistance.

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