Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts

a technology of double patterning and quantitative evaluation, applied in the field of methods for fabricating integrated circuits, can solve the problems of significant handicaps such as lack of evaluation methodologies, and achieve the effect of improving the score of metri

Active Publication Date: 2013-08-01
GLOBALFOUNDRIES US INC
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Benefits of technology

[0007]Methods are provided for fabricating an integrated circuit. In accordance with one embodiment, a method includes providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements and scoring the design of one or more of the plurality of elements to produce a design score. Once the design has been scored, the method may further include modifying the design based at least in part on the design score. Once the design has been finalized, the method may include generating a mask set implementing the modified logical design and employing the mask set to implement the logical design in and on a semiconductor substrate.
[0008]In accordance with a

Problems solved by technology

The lack of an evaluation methodology can be a significant handicap when comparing the p

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  • Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts
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  • Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts

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Embodiment Construction

[0024]The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

[0025]This invention establishes methods for fabricating an integrated circuit wherein a methodology to systematically quantify the quality of double patterning technology (DPT)-compliant layout designs for an integrated circuit in order to, for example, evaluate and provide guidance for any opportunistic layout modifications such that manufacturability- and yield-related issues can be improved. A DPT-optimized scoring methodology is provided to systematically, automatically, and quickly quantify the quality of DPT-compliant layouts. The score is assigned based on the layout design's robustness to a set of DPT-specific metrics.

[0026]Table ...

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Abstract

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Description

TECHNICAL FIELD[0001]The present invention generally relates to methods for fabricating an integrated circuit, and more particularly relates to methods that include scoring the quality of double patterning technology-compliant integrated circuit design layouts.BACKGROUND[0002]There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.[0003]High numeri...

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F17/5081G03F1/70G06F30/398
Inventor WANG, LYNN T.MADHAVAN, SRIRAMCAPODIECI, LUIGI
Owner GLOBALFOUNDRIES US INC
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