330 results about "Mask set" patented technology

A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and at least a second mask (310). The first mask provides features in a first grid pattern and the second mask provides features in a second grid pattern. The first and second grid pattern have respective features that interleave with one another over at least one area. A first photoresist film is applied onto the surface of the substrate (315). The first grid pattern is printed using the first mask (320). The second grid pattern is printed using the second mask (325). The first and said second grid pattern are then etched into the surface of the substrate (330). Another embodiment of the invention includes an integrated circuit (240) that has vias or contacts in a grid-like feature pattern in at least one multi-transistor area of the circuit including at least 5 transistors, wherein a minimum horizontal or minimum vertical center-to-center spacing distance between neighboring features in the pattern is ≦100 nm.

The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

A method of designing a double patterning mask set includes dividing a chip into a grid comprising grid cells; and laying out a metal layer of the chip. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first one of a first indicator and a second indicator, and all right-boundary patterns of the metal layer are assigned with a second one of the first indicator and the second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set, with all patterns assigned with the first indicator transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set.

The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.

The present invention discloses a mask assembly configured to prevent thermal deformation of a mask and maintain a gap between a plurality of divided pattern masks. According to one embodiment, the mask assembly includes: an opening mask having a plurality of first openings arranged in rows or columns; and a pattern mask including a plurality of unit pattern masks. In some embodiments, an end portion of a unit pattern mask including a plurality of mask pattern units configured to be aligned with a plurality of first openings of the open mask may be fixed relative to the open mask. In some embodiments, a pulling force is applied to the unit pattern mask.

A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.

A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

A deposition mask comprises a mask frame having an open window defined in a center thereof, a first mask sheet placed on the mask frame and including a plurality of open regions and a separation region which separates the open regions, and a second mask sheet placed on the first mask sheet and including a first aperture portion in a region which contacts the separation region of the first mask sheet.

A functional and decorative key mask is disclosed that is printable and has a uniquely functional geometry for easy and clean removable attachment to the keyfaces of a keyboard or keypad. The materials and design combine to provide a durable and reusable key mask. In the preferred embodiment, the key mask is has a body and a tab extending outward, and a pressure sensitive adhesive adhered to the back surface. It is die-cut from a face stock that is attached by the adhesive to a coated release liner. Mask sets include several key masks having similar or individualized graphic illustrations that enable the user to make unique associations with the keys of the keyboard or keypad, and thus enhance their learning, skill, performance, and enjoyment of a standard keyboard or keypad, or one having specialized key assignments.

One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer.

The invention provides a photomask, a method for manufacturing the photomask, and a pattern transfer method. An object of the invention is to provide a photomask such as a gray mask, which can restrain electrostatic destruction of pattern caused in treatment in mask use, even if electrostatic destruction is generated, mask design formed by an apparatus may not be affected in use. According to the invention, a photomask is provided on a transparent substrate (24) for forming desired mask patterns of the transfer patterns (such as gray masks), and conductive patterns separately guided from separated a plurality of mask designs (11a and 11b, 11c and 11d, 12a and 12b, 12c and 12d) are provided. The conductive patterns have non-contact parts nearer each other in comparison with each space between each mask pattern, which is formed by such as semitranslucent film or translucent film.

The invention discloses a mask set and a method for detecting the alignment precision by utilizing the mask set, and provides a novel mask set and a method for detecting the alignment precision by utilizing the mask set. The mask set comprises a first mask and at least one second mask; each second mask comprises one or more point positions for detecting the alignment precision; the area, corresponding to the point position, of the first mask is provided with at least one first alignment mark, and the first alignment mark is a line segment with a set length; the area, corresponding to the point positions, of the second mask is provided with second alignment marks corresponding to the first alignment marks one by one, and each second alignment mark is a line segment with a set length; the projection of the first alignment marks on the first mask is intersected with that of the second alignment marks on the first mask, and the projection of the first alignment mark and the projection of the second alignment mark form a set angle.

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

The invention discloses a masking system and method of timely communication information, which comprises the following parts: receiving unit, which receives the timely communication information, first display unit, which displays the timely communication information of linker and group in the non-masking condition to modify the condition of all linkers and group of user into non-masking condition during triggering demasking operation; temporary storage unit, which reserves the timely communication information of linker and group in the masking condition. The invention reduces the complex operation of mask setting for each link and group separately, which realizes the mask of all linker and group information through one-time masking operation.

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.

A mask set for forming a semiconductor device includes a universal mask used multiple times in the fabrication process. The universal mask may include contact structures, interconnect structures or both. For each level of use, the universal mask includes some features that provide connection between superjacent and subjacent features and other features that do not provide contact to superjacent or subjacent device features. When used at another level, the other features that did not provide contact between features in the previous location, may advantageously provide contact between superjacent and subjacent structures at the new level. A method for forming a semiconductor device using the described mask set is also provided. The invention further provides a computer program product that provides encoded instructions for forming such a mask set and an apparatus for receiving the instructions and forming the mask set.

According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a semiconductor device, mask sets for forming a semiconductor device, and a semiconductor device made according to various methods. For example, a method can comprise forming a first feature and a second feature on a substrate by exposing a first mask to a first beam, wherein the second feature is disposed adjacent to the first feature, exposing a second mask to a second beam, and removing the second feature from the substrate.