Methods for high temperature etching a high-k gate structure

a gate structure and high-temperature etching technology, applied in the direction of basic electric elements, electrical apparatus, semiconductor devices, etc., can solve the problems of silicon recesses, foot, or other associated defects on the interface of high-k materials, and materials that are difficult to etch during the gate structure manufacture sequence,

Inactive Publication Date: 2013-12-26
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This method achieves a smooth, vertical, and defect-free gate structure with improved selectivity over adjacent layers, maintaining the integrity of the high-k material profiles and reducing post-etch residues.

Problems solved by technology

However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities.
Although most high-k materials are relatively stable at ambient temperatures, these materials have proven to be difficult to etch during a gate structure manufacture sequence.
Additionally, conventional etchants have low selectivity to etch high-k materials over other materials present in the gate structure, such as gate electrode and / or underlying materials, thereby leaving silicon recess, foot, or other associated defects on the interface of the high-k materials over other materials.

Method used

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  • Methods for high temperature etching a high-k gate structure
  • Methods for high temperature etching a high-k gate structure
  • Methods for high temperature etching a high-k gate structure

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Embodiment Construction

[0021]The invention generally relates to methods for etching a high-k material that is part of a film stack suitable for gate structure fabrication. In one embodiment, the high-k material of the gate structure film stack is etched at a temperature between about 100 degrees Celsius and about 250 degrees Celsius. In another embodiment, the high-k material along with an adjacent gate electrode layer are both etched at the similar temperature between about 100 degrees Celsius and about 250 degrees Celsius. The process described herein is advantageously suitable for high-k containing gate structure applications having submicron critical dimensions. The process also preserves a smooth, vertical, foot-free, zero silicon recess and straight profile of the formed gate structure. The etching process may be sequentially performed in a single etching chamber.

[0022]The etch process described herein may be performed in any suitable plasma etch chamber, for example, a Decoupled Plasma Source (DPS)...

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Abstract

Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims benefit of U.S. Provisional Application Ser. No. 60 / 946,581, filed Jun. 27, 2007 (Attorney Docket No. APPM / 11146L), U.S. Provisional Application Ser. No. 60 / 987,159, filed Nov. 12, 2007 (Attorney Docket No. APPM / 11146L02), and United States Non-Provisional application Ser. No. 12 / 146,303, filed Jun. 25, 2008 (Attorney Docket No. APPM / 11146US), all of which are incorporated by reference in their entirety.BACKGROUND[0002]1. Field of the Invention[0003]Embodiments of the present invention generally relates to methods for high temperature etching of high-k materials, more specifically, for high temperature etching high-k materials during the fabrication of gate structures.[0004]2. Description of the Related Art[0005]Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconducto...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/3065
CPCH01L21/3065H01L21/31116H01L21/31122H01L21/32137H01L29/40117
InventorLIU, WEIMATSUSUE, EIICHISHEN, MEIHUADESHMUKH, SHASHANK C.PHAN, ANH-KIET QUANGPALAGASHVILI, DAVIDWILLWERTH, MICHAEL D.SHIN, JONG I.FINCH, BARRETTKAWASE, YOHEI
OwnerAPPLIED MATERIALS INC