Method for forming an electrical connection between metal layers

a metal layer and electrical connection technology, applied in the field of semiconductor processing, can solve the problems of increasing the resistance of the conductive via over time, via failure, and failure of the integrated circui

Inactive Publication Date: 2014-02-06
NXP USA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively reduces the risk of via failure by managing vacancy accumulation and ensuring the long-term reliability and integrity of the integrated circuit connections.

Problems solved by technology

However, stress migration over time may result in via failures within the integrated circuit.
For example, during operation of the integrated circuit, stress migration can cause the accumulation of vacancies within or at a conductive via, thus increasing the resistance of the conductive via over time.
Eventually, the increasing resistance due to the vacancies may cause via failure.
Stress migration may therefore affect long term operation and reliability of the integrated circuit.

Method used

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  • Method for forming an electrical connection between metal layers
  • Method for forming an electrical connection between metal layers
  • Method for forming an electrical connection between metal layers

Examples

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Embodiment Construction

[0017]As discussed above, stress migration can cause a via failure over time. Therefore, one embodiment of the present disclosure uses a geometry-based stress migration model of a circuit design to identify those vias in the circuit design which are at high risk for failing due to stress migration. In response to identification of a high risk via, one or more additional vias may be added to the circuit design to reduce the risk level of the via to an acceptable level for stress migration. Furthermore, electromigration can also cause via failure over time. Therefore, in one embodiment, one or more additional vias may be added to the circuit design to reduce the risk level of the via to an acceptable level for electromigration.

[0018]For example, FIG. 3 illustrates a cross section of a circuit 100 which includes a via 120 formed in a first metal layer 110 and which electrically contacts an underlying metal layer 104. As illustrated in FIG. 3, metal layer 104 may overlie a number of int...

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Abstract

A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) [0001]This application is related to U.S. patent application Ser. No. ______ (Attorney Docket No. MT11817TP), filed on even date, entitled “METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS,” naming Edward O. Travis, Douglas M. Reber, and Mehul D. Shroff as inventors, and assigned to the current assignee hereof.BACKGROUND [0002]1. Field[0003]This disclosure relates generally to semiconductor processing, and more specifically, to a method for forming an electrical connection between metal layers.[0004]2. Related Art[0005]Conductive vias provide electrical connections between metal layers of an integrated circuit. However, stress migration over time may result in via failures within the integrated circuit. For example, during operation of the integrated circuit, stress migration can cause the accumulation of vacancies within or at a conductive via, thus increasing the resistance of the conductive via over time. Eventually, the i...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/768
CPCG06F30/394H01L21/76816H01L23/5226H01L29/401H01L2924/0002H01L2924/00H01L21/4763H01L21/76877
InventorREBER, DOUGLAS M.SHROFF, MEHUL D.TRAVIS, EDWARD O.
OwnerNXP USA INC